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1. 发明授权

US07085865B2 I/O throughput by pre-termination arbitration 失效
标题翻译：通过预终止仲裁的I / O吞吐量
公开(公告)号：US07085865B2
公开(公告)日：2006-08-01
申请号：US10895654
申请日：2004-07-21
申请人： Juergen Haess , Ingemar Holm , Hartmut Ulland , Gerhard Zilles
发明人： Juergen Haess , Ingemar Holm , Hartmut Ulland , Gerhard Zilles
IPC分类号： G06F13/36 , G06F13/40 , G06F13/20 , G06F13/28
CPC分类号： G06F13/364
摘要： The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.
摘要翻译：本发明提供了一种经由总线系统发送数据的方法，该总线系统将多个总线参与者与多个总线参与者的仲裁程序相结合。本发明还允许在第一次传输期间的总线仲裁，因为总线可以在第一次传输之后被授权用于第二次传输，而不浪费总线周期。这是通过根据存储器边界和传输分组边界条件确定第一次传输剩余的周期数来实现的。

2. 发明申请

US20050060454A1 I/O throughput by pre-termination arbitration 失效
标题翻译：通过预终止仲裁的I / O吞吐量
公开(公告)号：US20050060454A1
公开(公告)日：2005-03-17
申请号：US10895654
申请日：2004-07-21
申请人： Juergen Haess , Ingemar Holm , Hartmut Ulland , Gerhard Zilles
发明人： Juergen Haess , Ingemar Holm , Hartmut Ulland , Gerhard Zilles
IPC分类号： G06F13/00 , G06F13/364
CPC分类号： G06F13/364
摘要： The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.
摘要翻译：本发明提供了一种经由总线系统发送数据的方法，该总线系统将多个总线参与者与多个总线参与者的仲裁程序相结合。本发明还允许在第一次传输期间的总线仲裁，因为总线可以在第一次传输之后被授权用于第二次传输，而不浪费总线周期。这是通过根据存储器边界和传输分组边界条件确定第一次传输剩余的周期数来实现的。

3. 发明授权

US5694400A Checking data integrity in buffered data transmission 失效
标题翻译：检查缓冲数据传输中的数据完整性
公开(公告)号：US5694400A
公开(公告)日：1997-12-02
申请号：US433410
申请日：1995-08-10
申请人： Gilles Gervais , Ingemar Holm , Helmut Kohler , Thomas Koehler , Norbert Schumacher , Gerhard Zilles
发明人： Gilles Gervais , Ingemar Holm , Helmut Kohler , Thomas Koehler , Norbert Schumacher , Gerhard Zilles
IPC分类号： G06F7/00 , G06F11/00 , G06F11/10 , G06F11/16 , G11C29/10 , G11C29/24
CPC分类号： G06F11/1008 , G06F11/0763 , G11C29/10 , G11C29/24 , G06F7/00
摘要： Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.
摘要翻译： PCT No.PCT / EP93 / 03572 Sec。 371日期：1995年8月10日 102（e）日期1995年8月10日PCT提交1993年12月15日PCT公布。公开号WO94 / 15290 日期1994年7月7日通过检查器（100）显示设备和检查方法。包含检查位的数据读入存储器堆栈。该装置包括通过逻辑门（30a-d）与一些存储器输入线（25）连接的第一计数器（20）和在检验器（100）和存储器（50）之间的第二计数器），其通过第一（20）和第二（80）通过逻辑门（70a-d）连接到与存储器输入线（25）对应的存储器输出线（55）。计数器产生连续的二进制值。该方法包括以下阶段：根据异或运算将待读取的数据与由第一计数器（20）生成的值的组合; 将逻辑组合数据读入存储器（50）; 从存储器（50）读取逻辑组合的数据; 根据异或运算，逻辑组合数据的读出与由第二计数器（80）生成的值的组合; 在奇偶校验器（100）中检查读出的奇偶校验数据。本发明可以用在两个异步定时总线之间的缓冲存储器（50）中。

4. 发明授权

US5321706A Method and apparatus for checking the address and contents of a memory array 失效
标题翻译：用于检查存储器阵列的地址和内容的方法和装置
公开(公告)号：US5321706A
公开(公告)日：1994-06-14
申请号：US719456
申请日：1991-06-24
申请人： Ingemar Holm , Helmut Kohler , Peter Mannherz , Norbert Schumacher , Gerhard Zilles
发明人： Ingemar Holm , Helmut Kohler , Peter Mannherz , Norbert Schumacher , Gerhard Zilles
IPC分类号： G06F12/16 , G06F11/10 , G06F11/00
CPC分类号： G06F11/1016 , G06F2201/88
摘要： A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.
摘要翻译：描述用于检查存储器阵列地址和内容的电路。电路由至少一个写地址计数器（120）和至少一个读地址计数器（130）组成。在将数据字读入阵列之前，其每个校验位与要写入该字的地址位置的一位进行异或运算。在读出该字时，校验位将再次与地址位置的位进行异或，以恢复其原始值，并检查数据字的奇偶校验。如果发现奇偶校验是不正确的，则知道在读入或读出时发生错误，并且可以采取适当的操作。

5. 发明授权

US07496692B2 Validating chip configuration data 失效
标题翻译：验证芯片配置数据
公开(公告)号：US07496692B2
公开(公告)日：2009-02-24
申请号：US11252533
申请日：2005-10-18
申请人： Ingemar Holm , Ralph C. Koester , John S. Liberty , Mack W. Riley
发明人： Ingemar Holm , Ralph C. Koester , John S. Liberty , Mack W. Riley
IPC分类号： G06F21/02
CPC分类号： G06F21/71
摘要： Verifying configuration data for configuring a microprocessor or system-on-a-chip (SoC) is provided. During initialization, configuration data is shifted into the microprocessor or SoC through a configuration input. The configuration data is shifted to all of the on-chip processor units to provide initial settings for configuration latches in the design. While the configuration data is being shifted to the on-chip processor units, a copy of the configuration data is also stored in a local storage of a test control unit. A private interface is provided between the test control unit and the processor units. Via the private interface, a processor unit receives the current configuration data for the processor units. The current configuration data is compared against the original configuration data stored in the test control unit to verify the current configuration of the processor units.
摘要翻译：提供了配置微处理器或片上系统（SoC）的配置数据。在初始化期间，配置数据通过配置输入移入微处理器或SoC。配置数据转移到所有片上处理器单元，以便为设计中的配置锁存器提供初始设置。当配置数据被转移到片上处理器单元时，配置数据的副本也存储在测试控制单元的本地存储器中。在测试控制单元和处理器单元之间提供专用接口。通过专用接口，处理器单元接收处理器单元的当前配置数据。将当前配置数据与存储在测试控制单元中的原始配置数据进行比较，以验证处理器单元的当前配置。

6. 发明授权

US07430624B2 High speed on-chip serial link apparatus and method 有权
标题翻译：高速片上串行连接装置及方法
公开(公告)号：US07430624B2
公开(公告)日：2008-09-30
申请号：US11242676
申请日：2005-10-04
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译：提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。因此，减少了本发明使用的复杂性和硅面积。该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

7. 发明申请

US20050099945A1 Combined and data compressed fifo based arbitration for a non-blocking switch 失效
标题翻译：用于非阻塞开关的组合和数据压缩基于fifo的仲裁
公开(公告)号：US20050099945A1
公开(公告)日：2005-05-12
申请号：US10425133
申请日：2003-04-28
申请人： Francois Abel , Gottfried Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
发明人： Francois Abel , Gottfried Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
IPC分类号： H04J3/14 , H04L12/56
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译：一种用于通过多输入（n）输出切换装置切换数据分组的方法和系统，其提供具有快速一周期吞吐量的切换方法。相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

8. 发明申请

US20090055637A1 SECURE POWER-ON RESET ENGINE 失效
标题翻译：安全上电复位发动机
公开(公告)号：US20090055637A1
公开(公告)日：2009-02-26
申请号：US11844449
申请日：2007-08-24
申请人： Ingemar Holm , Ralph C. Koester , Cedric Lichtenau , Thomas Pflueger , Mack W. Riley
发明人： Ingemar Holm , Ralph C. Koester , Cedric Lichtenau , Thomas Pflueger , Mack W. Riley
IPC分类号： G06F15/177
CPC分类号： G06F21/575 , G06F21/71
摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.
摘要翻译：在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。

9. 发明授权

US07379470B2 Combined and data compressed FIFO based arbitration for a non-blocking switch 失效
标题翻译：用于非阻塞开关的组合和数据压缩基于FIFO的仲裁
公开(公告)号：US07379470B2
公开(公告)日：2008-05-27
申请号：US10425133
申请日：2003-04-28
申请人： Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
发明人： Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
IPC分类号： H04L12/54
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译：一种用于通过多输入（n）输出切换装置切换数据分组的方法和系统，其提供具有快速一周期吞吐量的切换方法。相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

10. 发明申请

US20060107093A1 Algorithm to encode and compress array redundancy data 失效
标题翻译：编码和压缩阵列冗余数据的算法
公开(公告)号：US20060107093A1
公开(公告)日：2006-05-18
申请号：US10981156
申请日：2004-11-04
申请人： Irene Beattie , Ingemar Holm , Mack Riley
发明人： Irene Beattie , Ingemar Holm , Mack Riley
IPC分类号： G06F11/00
CPC分类号： G11C29/802
摘要： A method, an apparatus and a computer program product are provided for the compression of array redundancy data. Array redundancy data can be lengthy and take up a lot of space on a processor. This invention provides an algorithm that can compress array redundancy data for storage, and decompress and reload the array redundancy data at power-on of the processor. This compression algorithm saves a lot of space on the processor, which enables the processor to save power during operation, and function more efficiently. This algorithm also skips defective array redundancy data, which can be detrimental to the processor.
摘要翻译：提供了用于压缩阵列冗余数据的方法，装置和计算机程序产品。阵列冗余数据可能很长，并占用了处理器上的大量空间。本发明提供了一种可以压缩阵列冗余数据进行存储并在处理器上电时对阵列冗余数据进行解压缩和重新加载的算法。这种压缩算法在处理器上节省了大量的空间，这使得处理器能够在运行期间节省功耗，并且更有效地起作用。该算法还跳过有缺陷的阵列冗余数据，这可能对处理器有害。

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