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1. 发明授权

US07271448B2 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US07271448B2
公开(公告)日：2007-09-18
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

2. 发明申请

US20060180854A1 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US20060180854A1
公开(公告)日：2006-08-17
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
IPC分类号： H01L31/113
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

3. 发明申请

US20060154478A1 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US20060154478A1
公开(公告)日：2006-07-13
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

4. 发明授权

US07875547B2 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US07875547B2
公开(公告)日：2011-01-25
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

5. 发明授权

US07400401B2 Measuring low dielectric constant film properties during processing 有权
标题翻译：在加工期间测量低介电常数膜性能
公开(公告)号：US07400401B2
公开(公告)日：2008-07-15
申请号：US11096049
申请日：2005-03-31
申请人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
IPC分类号： G01J4/00
CPC分类号： G01N21/211
摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.
摘要翻译：用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质使用微波光谱仪恒定并导出介电常数的偶极分量。测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

6. 发明申请

US20060220653A1 Measuring low dielectric constant film properties during processing 有权
标题翻译：在加工期间测量低介电常数膜性能
公开(公告)号：US20060220653A1
公开(公告)日：2006-10-05
申请号：US11096049
申请日：2005-03-31
申请人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
IPC分类号： G01R31/00 , G01N21/00 , G01J4/00
CPC分类号： G01N21/211
摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.
摘要翻译：用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质使用微波光谱仪恒定并导出介电常数的偶极分量。测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

7. 发明申请

US20070222000A1 METHOD OF FORMING SILICIDED GATE STRUCTURE 审中-公开
标题翻译：形成硅胶结构的方法
公开(公告)号：US20070222000A1
公开(公告)日：2007-09-27
申请号：US11756131
申请日：2007-05-31
申请人： Bor-Wen Chan , Jyu-Horng Shieh , Hun-Jan Tao
发明人： Bor-Wen Chan , Jyu-Horng Shieh , Hun-Jan Tao
IPC分类号： H01L27/088
CPC分类号： H01L29/66507 , H01L21/28097
摘要： A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.
摘要翻译：提供了在具有活性区域的基板上形成硅化栅的方法。该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

8. 发明申请

US20070001306A1 Dual damascene interconnect in hybrid dielectric 有权
标题翻译：混合电介质中的双镶嵌互连
公开(公告)号：US20070001306A1
公开(公告)日：2007-01-04
申请号：US11172442
申请日：2005-06-30
申请人： Yi-Nien Su , Jyu-Horng Shieh , Hun-Jan Tao
发明人： Yi-Nien Su , Jyu-Horng Shieh , Hun-Jan Tao
IPC分类号： H01L23/52
CPC分类号： H01L21/76829 , H01L21/76808 , H01L21/7681 , H01L21/76832 , H01L21/76834 , H01L21/76835
摘要： A semiconductor device. A diffusion barrier layer overlies a substrate. An adhesion promoting layer overlies the diffusion barrier layer. A first dielectric layer between the diffusion barrier layer and the adhesion promoting layer comprises at least one via opening through the diffusion barrier layer and the adhesion promoting layer. A second dielectric layer overlies the adhesion promoting layer, comprising a trench opening above the via opening. A metal interconnect fills the via and trench openings.
摘要翻译：半导体器件。扩散阻挡层覆盖在基底上。粘附促进层覆盖在扩散阻挡层上。扩散阻挡层和增粘层之间的第一电介质层包括穿过扩散阻挡层和粘合促进层的至少一个通孔。第二电介质层覆盖粘附促进层，包括在通孔开口上方的沟槽开口。金属互连件填充通孔和沟槽开口。

9. 发明授权

US07598176B2 Method for photoresist stripping and treatment of low-k dielectric material 有权
标题翻译：光刻胶剥离和低k介电材料处理方法
公开(公告)号：US07598176B2
公开(公告)日：2009-10-06
申请号：US10949128
申请日：2004-09-23
申请人： Jang-Shiang Tsai , Yi-Nien Su , Chung-Chi Ko , Jyu-Horng Shieh , Peng-Fu Hsu , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Yi-Nien Su , Chung-Chi Ko , Jyu-Horng Shieh , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/311
CPC分类号： H01L21/02063 , G03F7/427 , Y10S438/958
摘要： A plasma processing operation uses a gas mixture of N2 and H2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carbon from the photoresist layer is activated and caused to complex with the low-k dielectric, maintaining a suitably high carbon content and a suitably low dielectric constant. The plasma processing operation uses a gas mixture with H2 constituting at least 10%, by volume, of the gas mixture.
摘要翻译：等离子体处理操作使用N 2和H 2的气体混合物来去除光致抗蚀剂膜并处理低k电介质材料。等离子体处理操作通过在低k电介质材料上形成保护层来防止低k材料的劣化。来自光致抗蚀剂层的碳被激活并与低k电介质复合，保持适当高的碳含量和合适的低介电常数。等离子体处理操作使用具有构成气体混合物的至少10体积％的H 2的气体混合物。

10. 发明授权

US07208331B2 Methods and structures for critical dimension and profile measurement 有权
标题翻译：关键尺寸和型材测量的方法和结构
公开(公告)号：US07208331B2
公开(公告)日：2007-04-24
申请号：US10949037
申请日：2004-09-24
申请人： Jyu-Horng Shieh , Wen-Chih Chiou , Peng-Fu Hsu , Baw-Ching Perng , Hun-Jan Tao , Chia-Jen Chen
发明人： Jyu-Horng Shieh , Wen-Chih Chiou , Peng-Fu Hsu , Baw-Ching Perng , Hun-Jan Tao , Chia-Jen Chen
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34
摘要： Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.
摘要翻译：公开了关键尺寸或轮廓测量的方法和结构。该方法提供其中具有周期性开口的基板。在开口中形成材料层，基本上平坦化基底的表面。将散射方法应用于具有临界尺寸（CD）或轮廓测量的材料层的基底。

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