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1. 发明申请

US20130003477A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件，包括备用抗体阵列和半导体存储器件的抗体修复方法
公开(公告)号：US20130003477A1
公开(公告)日：2013-01-03
申请号：US13534161
申请日：2012-06-27
申请人： Ju-Seop PARK , Sin Ho KIM , Byung-Sik MOON , Jong-Pil SON , Jin-Ho KIM , Hyoung-Joo KIM , Jong-Min OH , Seong-Jin JANG
发明人： Ju-Seop PARK , Sin Ho KIM , Byung-Sik MOON , Jong-Pil SON , Jin-Ho KIM , Hyoung-Joo KIM , Jong-Min OH , Seong-Jin JANG
IPC分类号： G11C11/21 , G11C29/44
CPC分类号： G11C29/027 , G11C29/789 , G11C29/808
摘要： A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells.
摘要翻译：提供了包括反熔丝电池阵列和备用反熔丝电池阵列的半导体存储器件。反熔丝电池阵列包括以第一方向布置的第一组反熔丝元件，并且第一组反熔丝电池中的每一个连接到第一至第n个字线中的对应的一个。备用反熔断电池阵列包括沿第一方向布置的第一备用组反熔丝单元，并且第一备用组反熔丝单元中的每一个连接到第一至第九备用字线中相应的一个。第一操作控制电路被配置为编制反冒点电池阵列和备用反熔丝电池阵列的反熔丝，并且读取每个反熔丝的状态。第一操作控制电路通常连接到第一组反熔丝电池和第一备用反熔丝电池组。

2. 发明申请

US20120039140A1 FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：保险丝电路和包括其的半导体存储器件
公开(公告)号：US20120039140A1
公开(公告)日：2012-02-16
申请号：US13205966
申请日：2011-08-09
申请人： Jin-Ho KIM , Jong-Pil SON , Seong-Jin JANG , Byung-Sik MOON , Seung-Hoon OH , Ju-Seop PARK
发明人： Jin-Ho KIM , Jong-Pil SON , Seong-Jin JANG , Byung-Sik MOON , Seung-Hoon OH , Ju-Seop PARK
IPC分类号： G11C29/04 , G11C17/16
CPC分类号： G11C29/027 , G11C17/16 , G11C29/04
摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.
摘要翻译：熔丝电路包括程序单元，感测单元和控制单元。程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。程序单元可以基于验证结果重新编程。

3. 发明申请

US20160055056A1 MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION 有权
标题翻译：具有错误通知功能的存储器
公开(公告)号：US20160055056A1
公开(公告)日：2016-02-25
申请号：US14729656
申请日：2015-06-03
申请人： Jong-Pil SON , Chul-Woo PARK , Seong-Jin JANG , Hoi-Ju CHUNG , Sang-Uhn CHA
发明人： Jong-Pil SON , Chul-Woo PARK , Seong-Jin JANG , Hoi-Ju CHUNG , Sang-Uhn CHA
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1024 , G06F11/1068 , G06F11/1666 , G11C2029/0411
摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.
摘要翻译：具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

4. 发明申请

US20160062830A1 SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME 有权
标题翻译：半导体存储器件，包括其的存储器系统和校正其中的错误的方法
公开(公告)号：US20160062830A1
公开(公告)日：2016-03-03
申请号：US14729295
申请日：2015-06-03
申请人： Sang-Uhn CHA , Hoi-Ju CHUNG , Jong-Pil SON , Kwang-Il PARK , Seong-Jin JANG
发明人： Sang-Uhn CHA , Hoi-Ju CHUNG , Jong-Pil SON , Kwang-Il PARK , Seong-Jin JANG
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G11C29/52 , G06F11/1048 , G11C11/15 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C29/702 , G11C2029/0411 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.
摘要翻译：半导体存储器件包括其中布置有多个存储器单元的存储单元阵列。半导体存储器件包括：纠错码（ECC）电路，被配置为基于主数据产生奇偶校验数据，将包括主数据和奇偶校验数据的码字写入存储单元阵列，将所选择的存储单元行的码字读取到产生综合征，并且基于每个符号基于综合征来校正读取的码字中的错误。主数据包括所选存储单元行的第一存储单元的第一数据和所选存储单元行的第二存储单元的第二数据。将第一数据和第二数据分配给多个符号的一个符号，并且第一存储单元和第二存储单元在存储单元阵列中彼此相邻。

5. 发明申请

US20110122711A1 BITLINE PRECHARGE VOLTAGE GENERATOR, SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME, AND METHOD OF TRIMMING BITLINE PRECHARGE VOLTAGE 有权
标题翻译：双列线式前置电压发生器，包含其的半导体存储器件以及双向预调电压调节方法
公开(公告)号：US20110122711A1
公开(公告)日：2011-05-26
申请号：US12904302
申请日：2010-10-14
申请人： Ki-Heung KIM , Seong-Jin JANG , Myeong-O KIM , Hong-Jun LEE , Tae-Yoon LEE
发明人： Ki-Heung KIM , Seong-Jin JANG , Myeong-O KIM , Hong-Jun LEE , Tae-Yoon LEE
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C11/4094 , G11C7/12 , G11C11/4074 , G11C29/02 , G11C29/028 , G11C2029/1204
摘要： A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.
摘要翻译：位线预充电电压发生器包括泄漏修整单元和位线预充电电压提供单元。泄漏修整单元向输出节点施加泄漏电流以将位线预充电电压置于死区的边缘。位线预充电电压提供单元向输出节点提供位线预充电电压，并将位线预充电电压设置为目标电平。位线预充电电压发生器产生具有包括死区的分布的位线预充电电压。

6. 发明申请

US20130003479A1 SEMICONDUCTOR MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权
标题翻译：半导体存储器单元阵列和具有该阵列的半导体存储器件
公开(公告)号：US20130003479A1
公开(公告)日：2013-01-03
申请号：US13616039
申请日：2012-09-14
申请人： Sang-Woong SHIN , Seong-Jin JANG
发明人： Sang-Woong SHIN , Seong-Jin JANG
IPC分类号： G11C7/06
CPC分类号： G11C7/02 , G11C7/14 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C11/4099 , G11C29/24
摘要： A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage
摘要翻译：半导体存储单元阵列包括多个位线，多个字线，多个存储单元，多个虚拟存储单元，多个虚拟位线和多个虚拟字线。虚拟位线位于位线的外部区域。虚拟字线在字线的外部区域。虚拟位线保持在浮置状态。虚拟字线保持关闭电压

7. 发明申请

US20070188201A1 SMALL SWING SIGNAL RECEIVER FOR LOW POWER CONSUMPTION AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：用于低功耗的小触发信号接收器和包括其的半导体器件
公开(公告)号：US20070188201A1
公开(公告)日：2007-08-16
申请号：US11566651
申请日：2006-12-04
申请人： Hyun-Jin KIM , Seong-Jin JANG , Kwang-Il PARK , Woo-Jin LEE
发明人： Hyun-Jin KIM , Seong-Jin JANG , Kwang-Il PARK , Woo-Jin LEE
IPC分类号： H03B1/00
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.
摘要翻译：一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。

8. 发明申请

US20070121418A1 CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 有权
标题翻译：在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US20070121418A1
公开(公告)日：2007-05-31
申请号：US11560746
申请日：2006-11-16
申请人： Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
发明人： Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

9. 发明申请

US20080225626A1 CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 有权
标题翻译：在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US20080225626A1
公开(公告)日：2008-09-18
申请号：US12128464
申请日：2008-05-28
申请人： Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
发明人： Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
IPC分类号： G11C8/10
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

10. 发明申请

US20080123454A1 CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：用于消除半导体集成电路中信号之间的晶体管的电路和方法
公开(公告)号：US20080123454A1
公开(公告)日：2008-05-29
申请号：US11770766
申请日：2007-06-29
申请人： Seung-Jun BAE , Kwang-Il PARK , Seong-Jin JANG
发明人： Seung-Jun BAE , Kwang-Il PARK , Seong-Jin JANG
IPC分类号： G11C7/02
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.
摘要翻译：一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移的半导体存储器件。

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