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1. 发明申请

US20110268202A1 TRANSMISSION UNIT ADOPTING A DIFFERENTIAL VOLTAGE DRIVING SYSTEM, TRANSMISSION UNIT AND RECEIVING UNIT SELECTIVELY ADOPTING A DIFFERENTIAL CURRENT DRIVING SYSTEM, DIFFERENTIAL VOLTAGE DRIVING SYSTEM, AND INTERFACE SYSTEM 有权
标题翻译：传输单元采用差分电压驱动系统，传输单元和接收单元选择采用差分电流驱动系统，差分电压驱动系统和接口系统
公开(公告)号：US20110268202A1
公开(公告)日：2011-11-03
申请号：US13142409
申请日：2009-12-03
申请人： Ju-Pyo Hong , Jun-Ho Kim , Jung-Hwan Choi
发明人： Ju-Pyo Hong , Jun-Ho Kim , Jung-Hwan Choi
IPC分类号： H04L27/00 , H04L25/06 , H04L27/04
CPC分类号： H04L25/0272 , H03K19/017581 , H04L7/0091 , H04L7/041 , H04L25/0282
摘要： In the transmitter, receiver and interface system capable of selective adoption of a differential current driving scheme and a differential voltage driving scheme, a differential current driving scheme and a differential voltage driving scheme can be selectively adopted in one semiconductor chip depending upon the states of the transmission lines, so that effective data transmission is possible and common parts can be shared, whereby a design time can be shortened and a layout area can be reduced.
摘要翻译：在能够选择性地采用差分电流驱动方案和差分电压驱动方案的发射器，接收器和接口系统中，可以在一个半导体芯片中选择性地使用差分电流驱动方案和差分电压驱动方案，这取决于传输线，使得有效的数据传输是可能的，并且可以共享公共部分，从而可以缩短设计时间并且可以减少布局面积。

2. 发明申请

US20110267022A1 INTERFACE SYSTEM FOR A COG APPLICATION 有权
标题翻译：用于COG应用的界面系统
公开(公告)号：US20110267022A1
公开(公告)日：2011-11-03
申请号：US13142413
申请日：2009-12-28
申请人： Ju-Pyo Hong , Jung-Hwan Choi , Jun-Ho Kim
发明人： Ju-Pyo Hong , Jung-Hwan Choi , Jun-Ho Kim
IPC分类号： G05F5/00
CPC分类号： H03K19/018528 , H04L25/0272 , H04L25/028
摘要： A current driving type transmitter using independent current signals, which can independently generate and transmit differential current indicating a logic state of data to be transmitted, using a difference between positive data current and negative data current without using external current, so that magnitudes of current applied to a pair of transmission lines can be kept constant without being influenced by the design of current sources and processing factors, a current driving type receiver using independent current signals, which can simultaneously convert a difference in levels of current, received through the transmission lines, into a voltage level by a single I-V converter, so that errors of a true line and a bar line can be lessened, and an interface system for COG application, which adopts the transmitter and receiver, so that distortion of transmitted signals can be reduced.
摘要翻译：使用独立电流信号的电流驱动型发射器，其可以使用正数据电流和负数据电流之间的差异独立地产生和发送指示要发送的数据的逻辑状态的差分电流，而不使用外部电流，使得施加的电流大小一对传输线可以保持恒定，而不受电流源和处理因素的设计的影响，使用独立电流信号的电流驱动型接收器可以同时转换通过传输线接收的电流差异，通过单个IV转换器进入电压电平，从而可以减少真线和条线的误差，以及采用发射机和接收机的COG应用的接口系统，从而可以减少发射信号的失真。

3. 发明授权

US08842745B2 Transmission unit adopting a differential voltage driving system, transmission unit and receiving unit selectively adopting a differential current driving system, differential voltage driving system, and interface system 有权
标题翻译：采用差分电压驱动系统的传输单元，选择采用差动电流驱动系统的传输单元和接收单元，差分电压驱动系统和接口系统
公开(公告)号：US08842745B2
公开(公告)日：2014-09-23
申请号：US13142409
申请日：2009-12-03
申请人： Ju-Pyo Hong , Jun-Ho Kim , Jung-Hwan Choi
发明人： Ju-Pyo Hong , Jun-Ho Kim , Jung-Hwan Choi
IPC分类号： H04L27/00 , H04L25/02 , H04L7/00 , H03K19/0175 , H04L7/04
CPC分类号： H04L25/0272 , H03K19/017581 , H04L7/0091 , H04L7/041 , H04L25/0282
摘要： In the transmitter, receiver and interface system capable of selective adoption of a differential current driving scheme and a differential voltage driving scheme, a differential current driving scheme and a differential voltage driving scheme can be selectively adopted in one semiconductor chip depending upon the states of the transmission lines, so that effective data transmission is possible and common parts can be shared, whereby a design time can be shortened and a layout area can be reduced.
摘要翻译：在能够选择性地采用差分电流驱动方案和差分电压驱动方案的发射器，接收器和接口系统中，可以在一个半导体芯片中选择性地使用差分电流驱动方案和差分电压驱动方案，这取决于传输线，使得有效的数据传输是可能的，并且可以共享公共部分，从而可以缩短设计时间并且可以减少布局面积。

4. 发明授权

US08400194B2 Interface system for a cog application 有权
标题翻译：用于cog应用程序的接口系统
公开(公告)号：US08400194B2
公开(公告)日：2013-03-19
申请号：US13142413
申请日：2009-12-28
申请人： Ju-Pyo Hong , Jung-Hwan Choi , Jun-Ho Kim
发明人： Ju-Pyo Hong , Jung-Hwan Choi , Jun-Ho Kim
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272 , H04L25/028
摘要： A current driving type transmitter using independent current signals, which can independently generate and transmit differential current indicating a logic state of data to be transmitted, using a difference between positive data current and negative data current without using external current, so that magnitudes of current applied to a pair of transmission lines can be kept constant without being influenced by the design of current sources and processing factors, a current driving type receiver using independent current signals, which can simultaneously convert a difference in levels of current, received through the transmission lines, into a voltage level by a single I-V converter, so that errors of a true line and a bar line can be lessened, and an interface system for COG application, which adopts the transmitter and receiver, so that distortion of transmitted signals can be reduced.
摘要翻译：使用独立电流信号的电流驱动型发射器，其可以使用正数据电流和负数据电流之间的差异独立地产生和发送指示要发送的数据的逻辑状态的差分电流，而不使用外部电流，使得施加的电流大小一对传输线可以保持恒定，而不受电流源和处理因素的设计的影响，使用独立电流信号的电流驱动型接收器可以同时转换通过传输线接收的电流差异，通过单个IV转换器进入电压电平，从而可以减少真线和条线的误差，以及采用发射机和接收机的COG应用的接口系统，从而可以减少发射信号的失真。

5. 发明授权

US08819790B2 Cooperation method and system between send mechanism and IPSec protocol in IPV6 environment 有权
标题翻译： IPV6环境下的发送机制与IPSec协议的协作方法和系统
公开(公告)号：US08819790B2
公开(公告)日：2014-08-26
申请号：US12040355
申请日：2008-02-29
申请人： Young-Ik Eom , Kwang-Sun Ko , Hyun-Su Jang , Hyun-jin Cho , Yong-Woo Jung , Hyun-Woo Choi , Gye-Hyeon Gyeong , Jung-Hwan Choi , Zhen Zhao , Tae-Hyoung Kim , Youn-Woo Kim
发明人： Young-Ik Eom , Kwang-Sun Ko , Hyun-Su Jang , Hyun-jin Cho , Yong-Woo Jung , Hyun-Woo Choi , Gye-Hyeon Gyeong , Jung-Hwan Choi , Zhen Zhao , Tae-Hyoung Kim , Youn-Woo Kim
IPC分类号： H04L9/32 , G06F21/00 , H04L29/06
CPC分类号： H04L63/164
摘要： The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec. The present invention allows the authentication information shared between SEND and IPSec in a mobile environment, where the network is frequently accessed, enabling IPSec secure communication at a lower cost.
摘要翻译：本发明涉及在IPv6环境中体现SEND与IPSec之间的协作系统的方法。根据本发明的SEND和IPSec之间的协作系统包括：接收认证完成报告消息，该消息包括通过SEND完成认证的主机的第一IP地址; 生成与所述主机对应的新认证信息，并将所述新认证信息存储在临时存储区域中，如果所述主机的认证信息不存在于所述临时存储区域中，则所述认证信息包括所述第一IP地址; 并且如果从IPSec接收到包含第二IP地址的认证检查请求消息，则检查该临时存储区域中是否存在第二IP地址，并向IPSec发送检查结果。本发明允许在经常访问网络的移动环境中在SEND和IPSec之间共享的认证信息以更低的成本实现IPSec安全通信。

6. 发明授权

US08661276B2 Apparatus and method for power control of a central processing unit in a multi-core system 有权
标题翻译：多核系统中央处理单元的功率控制装置及方法
公开(公告)号：US08661276B2
公开(公告)日：2014-02-25
申请号：US12909417
申请日：2010-10-21
申请人： Ji-Hwan Park , Hyun-Moo Kim , Nam-Su Ha , Jung-Hwan Choi , Jin-Hyo Kim , Tae-Il Kim , Il-Hyun Cho , Sung-Joon Jang , Hye-Sun Kim , Jin-Kyoung Du
发明人： Ji-Hwan Park , Hyun-Moo Kim , Nam-Su Ha , Jung-Hwan Choi , Jin-Hyo Kim , Tae-Il Kim , Il-Hyun Cho , Sung-Joon Jang , Hye-Sun Kim , Jin-Kyoung Du
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/172
摘要： A power control method of a Central Processing Unit (CPU) in a multi-core system. The power control method includes acquiring current usage information of the CPU and system information, estimating a CPU usage of a next time interval based on the acquired current usage information, calibrating the estimated CPU usage of the next time interval based on the acquired system information, and determining a power control mode based on at least one of the acquired system information and the calibrated CPU usage of the next time interval.
摘要翻译：多核系统中的中央处理单元（CPU）的功率控制方法。功率控制方法包括获取CPU的当前使用信息和系统信息，基于获取的当前使用信息估计下一时间间隔的CPU使用量，基于获取的系统信息校准下一时间间隔的估计CPU使用量，以及基于所获取的系统信息和下一时间间隔的校准CPU使用中的至少一个来确定功率控制模式。

7. 发明授权

US07131042B2 Semiconductor device and method for testing the same 有权
标题翻译：半导体装置及其测试方法
公开(公告)号：US07131042B2
公开(公告)日：2006-10-31
申请号：US10421533
申请日：2003-04-21
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G01R31/28
CPC分类号： G01R31/31926
摘要： Test board configurations and test method for semiconductor devices with simultaneous bi-directional (SBD) data ports are disclosed. The devices have two SBD data ports with a pass mode that relays data between the ports. Significantly, each device contains configurable switching elements that allow a test mode, wherein unidirectional input/output data on one SBD data port is mapped to bi-directional data on the other SBD data port. This allows device testing with automated test equipment that employs unidirectional data signaling, and yet allows such test equipment to test the SBD capability of such devices.
摘要翻译：公开了具有同时双向（SBD）数据端口的半导体器件的测试板配置和测试方法。这些设备具有两个SBD数据端口，通过模式在端口之间中继数据。重要的是，每个设备都包含允许测试模式的可配置开关元件，其中一个SBD数据端口上的单向输入/输出数据映射到另一个SBD数据端口上的双向数据。这允许使用采用单向数据信号的自动测试设备进行设备测试，并允许这种测试设备测试这些设备的SBD能力。

8. 发明授权

US07023742B2 Semiconductor device and method for inputting/outputting data simultaneously through single pad 有权
标题翻译：半导体装置和通过单个焊盘同时输入/输出数据的方法
公开(公告)号：US07023742B2
公开(公告)日：2006-04-04
申请号：US10819678
申请日：2004-04-06
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C11/4093 , G11C2207/005 , G11C2207/105
摘要： Provided are a semiconductor device and a method for inputting and outputting data simultaneously through a single bi-directional pad. The semiconductor device includes a bi-directional input/output pad including an output buffer and an input buffer, a data output line coupled to the output buffer, and a data input line coupled to the input buffer. A bit line sense amplifier is coupled to a plurality of bit lines. A first switching circuit is coupled to the data output line. And a second switching circuit is coupled to the data input line.
摘要翻译：提供了一种通过单个双向键盘同时输入和输出数据的半导体器件和方法。半导体器件包括双向输入/输出焊盘，其包括输出缓冲器和输入缓冲器，耦合到输出缓冲器的数据输出线以及耦合到输入缓冲器的数据输入线。位线读出放大器耦合到多个位线。第一开关电路耦合到数据输出线。并且第二开关电路耦合到数据输入线。

9. 发明授权

US06859078B2 Delay lock loop circuit 有权
标题翻译：延时锁回路电路
公开(公告)号：US06859078B2
公开(公告)日：2005-02-22
申请号：US10641313
申请日：2003-08-14
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： H03L7/22 , H03L7/07 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/07
摘要： A delay lock loop circuit includes a reference loop for receiving an external clock signal and for generating a second output signal and a first output signal which includes a plurality of signals having different respective phases. A fine loop receives the external clock signal and the first output signal of the reference loop and generates an internal clock signal. A transition detecting circuit receives the second output signal of the reference loop and generates a protection signal by detecting a transition of the logic state of the second output signal of the reference loop. In response to the protection signal, the delay lock loop circuit in accordance with the present invention protects itself from an external clock signal that has a frequency that is out of the range of operable frequencies of the delay lock loop circuit, for example by disabling the entire circuit, or a portion of the circuit.
摘要翻译：延迟锁定环电路包括用于接收外部时钟信号并用于产生第二输出信号的参考回路和包括具有不同相位相位的多个信号的第一输出信号。精细回路接收外部时钟信号和参考环路的第一个输出信号，并产生内部时钟信号。转移检测电路接收参考回路的第二输出信号，并通过检测参考回路的第二输出信号的逻辑状态的转变来产生保护信号。响应于保护信号，根据本发明的延迟锁定环路电路保护自身不具有超出延迟锁定环电路的可操作频率范围的频率的外部时钟信号，例如通过禁用整个电路或电路的一部分。

10. 发明授权

US06839786B2 Information processing system with memory modules of a serial bus architecture 有权
标题翻译：具有串行总线结构的存储器模块的信息处理系统
公开(公告)号：US06839786B2
公开(公告)日：2005-01-04
申请号：US10166258
申请日：2002-06-11
申请人： Kyung-Ho Kim , Jung-Hwan Choi , Nak-Won Heo
发明人： Kyung-Ho Kim , Jung-Hwan Choi , Nak-Won Heo
IPC分类号： G06F13/00 , G11C7/10 , G11C11/4076 , G11C11/409 , G06F1/04
CPC分类号： G11C11/409 , G11C7/1048 , G11C11/4076
摘要： An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.

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