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1. 发明申请

US20050270058A1 System for testing integrated circuit devices 审中-公开
标题翻译：集成电路设备测试系统
公开(公告)号：US20050270058A1
公开(公告)日：2005-12-08
申请号：US11200372
申请日：2005-08-09
申请人： Joseph Sher , David Siek , Huy Vo , Nicholas Van Heel , Victor Wong , Hua Zheng
发明人： Joseph Sher , David Siek , Huy Vo , Nicholas Van Heel , Victor Wong , Hua Zheng
IPC分类号： G01R31/26 , G01R31/30 , G11C5/14 , G11C29/02 , G11C29/12
CPC分类号： G11C29/02 , G01R31/3004 , G11C5/145 , G11C5/146 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C2029/5004
摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.
摘要翻译：用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。电压产生电路允许通过常规测试功能在执行标准中通过施加测试信号来外部控制存储器件的内部产生的电压，例如衬底电压Vbb，DVC 2电压和泵浦电压Vccp。诸如静态刷新测试，逻辑1s和0s边缘测试等设备测试等，用于封装的存储器件。此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

2. 发明授权

US06459634B1 Circuits and methods for testing memory cells along a periphery of a memory array 有权
标题翻译：沿着存储器阵列周边测试存储器单元的电路和方法
公开(公告)号：US06459634B1
公开(公告)日：2002-10-01
申请号：US09495055
申请日：2000-01-31
申请人： Joseph Sher
发明人： Joseph Sher
IPC分类号： G11C700
CPC分类号： G11C29/18 , G11C29/24
摘要： A memory device comprising an array of memory cells includes test circuitry which is selectively configurable to interchangeably couple a dummy cell, which neighbors a memory cell at an edge of the array, to a select one of a plurality of different voltages. In a preferred embodiment, the test circuitry is configurable to selectively couple the dummy cell to one of an upper, lower or intermediate supply bus.
摘要翻译：包括存储器单元阵列的存储器件包括测试电路，其被选择性地配置为可互换地将与阵列边缘处的存储单元相邻的虚拟单元可互换地耦合到多个不同电压中的选择一个。在优选实施例中，测试电路可配置为将虚拟单元选择性地耦合到上，下或中间供电总线之一。

3. 发明授权

US6055191A Method and apparatus for leakage blocking 有权
标题翻译：泄漏堵塞的方法和装置
公开(公告)号：US6055191A
公开(公告)日：2000-04-25
申请号：US225133
申请日：1999-01-04
申请人： Joseph Sher , Dan Loughmiller
发明人： Joseph Sher , Dan Loughmiller
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051
摘要： A method and apparatus for applying a blocking potential for gating inputs of pull-up and pull-down devices of an output driver is described. The blocking potential is applied to either or both of a pull-up or pull-down transistor for reducing leakage current. In particular, a circuit having a voltage generator for producing the blocking polarity potential is connected to a voltage translator. A control signal is provided to the voltage translator for accessing the output driver. During accessing of the output driver, the blocking polarity potential is isolated from gating inputs of the pull-up and pull-down devices of the output driver. In a memory device employing the output driver, the blocking polarity potential is applied when the memory is in a state which does not activate the output driver. The blocking polarity is provided by a voltage divider using a substrate bias potential. A feedback path is employed to follow voltage applied to an output pad through substrate bias voltage.
摘要翻译：描述了用于对输出驱动器的上拉和下拉装置的门控输入施加阻塞电位的方法和装置。阻塞电位被施加到上拉或下拉晶体管中的一个或两者以减少泄漏电流。特别地，具有用于产生阻挡极性电位的电压发生器的电路连接到电压转换器。控制信号提供给电压转换器以访问输出驱动器。在访问输出驱动器期间，阻塞极性电位与输出驱动器的上拉和下拉器件的门控输入隔离。在采用输出驱动器的存储器件中，当存储器处于不激活输出驱动器的状态时，施加阻挡极性电位。阻挡极性由使用衬底偏置电位的分压器提供。采用反馈路径来跟随通过衬底偏置电压施加到输出焊盘的电压。

4. 发明授权

US5914898A Memory device and system with leakage blocking circuitry 失效
标题翻译：具有泄漏阻塞电路的存储器件和系统
公开(公告)号：US5914898A
公开(公告)日：1999-06-22
申请号：US906568
申请日：1997-08-05
申请人： Joseph Sher , Dan Loughmiller
发明人： Joseph Sher , Dan Loughmiller
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051
摘要： A method and apparatus for applying a blocking potential for gating inputs of pull-up and pull-down devices of an output driver is described. The blocking potential is applied to either or both of a pull-up or pull-down transistor for reducing leakage current. In particular, a circuit having a voltage generator for producing the blocking polarity potential is connected to a voltage translator. A control signal is provided to the voltage translator for accessing the output driver. During accessing of the output driver, the blocking polarity potential is isolated from gating inputs of the pull-up and pull-down devices of the output driver. In a memory device employing the output driver, the blocking polarity potential is applied when the memory is in a state which does not activate the output driver. The blocking polarity is provided by a voltage divider using a substrate bias potential. A feedback path is employed to follow voltage applied to an output pad through substrate bias voltage.
摘要翻译：描述了用于对输出驱动器的上拉和下拉装置的门控输入施加阻塞电位的方法和装置。阻塞电位被施加到上拉或下拉晶体管中的一个或两者以减少泄漏电流。特别地，具有用于产生阻挡极性电位的电压发生器的电路连接到电压转换器。控制信号提供给电压转换器以访问输出驱动器。在访问输出驱动器期间，阻塞极性电位与输出驱动器的上拉和下拉器件的门控输入隔离。在采用输出驱动器的存储器件中，当存储器处于不激活输出驱动器的状态时，施加阻挡极性电位。阻挡极性由使用衬底偏置电位的分压器提供。采用反馈路径来跟随通过衬底偏置电压施加到输出焊盘的电压。

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