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1. 发明申请

US20070153445A1 Integrated circuit passive signal distribution 有权
标题翻译：集成电路无源信号分配
公开(公告)号：US20070153445A1
公开(公告)日：2007-07-05
申请号：US11323370
申请日：2005-12-29
申请人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen Mooney
发明人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen Mooney
IPC分类号： H02B1/00
CPC分类号： H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。内部传输线路可以将信号被动地发送到内部传输线路的第二端。集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入线接收信号。第二位置可以不同于第一位置。还公开了其他实施例。

2. 发明申请

US20060110952A1 Systems for interchip communication 审中-公开
标题翻译：芯片间通信系统
公开(公告)号：US20060110952A1
公开(公告)日：2006-05-25
申请号：US10995851
申请日：2004-11-22
申请人： Shekhar Borkar , Matthew Haycock , Stephen Mooney , Aaron Martin , Joseph Kennedy
发明人： Shekhar Borkar , Matthew Haycock , Stephen Mooney , Aaron Martin , Joseph Kennedy
IPC分类号： H05K1/00
CPC分类号： G06F13/4086
摘要： In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.
摘要翻译：在一些实施例中，本发明涉及具有以截头环方式连接的第一组集成电路的系统，其中所述截头环包括截取的区域，以允许将额外的集成电路添加到所述环中。在一些实施例中，本发明涉及具有以伪环方式连接的一组集成电路的系统，其中通过集成电路之间的双向信令的数据流创建伪环。在一些实施例中，本发明涉及一种具有以伪差分布置连接的一组集成电路的系统，其中携带多个导体的信号共用公共参考信号导体。

3. 发明申请

US20050146919A1 Memory system segmented power supply and control 失效
标题翻译：内存系统分段供电和控制
公开(公告)号：US20050146919A1
公开(公告)日：2005-07-07
申请号：US10748460
申请日：2003-12-29
申请人： Robert Ellis , Stephen Mooney , Joseph Kennedy
发明人： Robert Ellis , Stephen Mooney , Joseph Kennedy
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C11/24
CPC分类号： G11C11/406 , G11C5/14 , G11C11/4074 , G11C2207/104 , G11C2211/4067
摘要： A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.
摘要翻译：具有被提供有比提供给存储器逻辑的单独功率分开的更高电压功率的存储单元的存储器件，以及需要从逻辑中的至少一些去除功率的较低功率状态，使得刷新操作以保持存储器单元的内容继续发生，但至少有一些到存储器件的接口掉电以降低功耗。

4. 发明申请

US20050237828A1 Distributed loop components 有权
标题翻译：分布式环路组件
公开(公告)号：US20050237828A1
公开(公告)日：2005-10-27
申请号：US10833966
申请日：2004-04-27
申请人： Joseph Kennedy , Stephen Mooney
发明人： Joseph Kennedy , Stephen Mooney
IPC分类号： G06F1/10 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0812
摘要： In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括用于从芯片外部接收延迟控制信号的芯片接口。芯片还包括可控延迟线，以响应于延迟控制信号来延迟输入信号，以提供具有与输入信号的特定相位关系的输出信号。描述和要求保护其他实施例。

5. 发明申请

US20050146980A1 Fixed phase clock and strobe signals in daisy chained chips 失效
标题翻译：在菊花链芯片中固定相位时钟和选通信号
公开(公告)号：US20050146980A1
公开(公告)日：2005-07-07
申请号：US10749677
申请日：2003-12-30
申请人： Stephen Mooney , Joseph Kennedy
发明人： Stephen Mooney , Joseph Kennedy
IPC分类号： G04G99/00 , G06F13/16 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/10 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C7/1093
摘要： In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括分别提供第一和第二接收数据信号以及第一和第二接收选通信号的第一和第二端口。内部时钟信号与第一接收选通信号具有固定的相位关系，第二接收选通信号与内部时钟信号具有任意的相位关系。第一和第二写入块分别与第一和第二接收选通信号同步地锁存第一和第二接收数据信号。描述和要求保护其他实施例。

6. 发明授权

US07100160B2 Method and system for implementing host-dependent SCSI behavior in a heterogeneous host environment 有权
公开(公告)号：US07100160B2
公开(公告)日：2006-08-29
申请号：US09981906
申请日：2001-10-19
申请人： Marc LeFevre , Stephen Mooney , Randy J. Matthews
发明人： Marc LeFevre , Stephen Mooney , Randy J. Matthews
IPC分类号： G06F9/46 , G06F9/00 , G06F12/00 , G06F13/00
CPC分类号： G06F13/4221
摘要： A method, system, and program product is provided for configuring a target device, the method comprising the steps of: receiving a log-in request to connect the target device to a host, wherein the log-in request includes a host designator; accessing a table of host designators and associated O/S types; determining if there is a match of the log-in request host designator to a host designator in the table; and selecting an O/S type protocol associated with the match to the host designator. In a preferred embodiment of the present invention, the host designator is a worldwide name. In a further embodiment of the present invention, the step is provided of determining if a mode parameter is set for a default O/S protocol; and selecting that default O/S protocol unless there is a match of the log-in request host designator in the table.

7. 发明授权

US07032029B1 Method and apparatus for an active standby control system on a network 有权
标题翻译：网络上主动备用控制系统的方法和装置
公开(公告)号：US07032029B1
公开(公告)日：2006-04-18
申请号：US09612636
申请日：2000-07-07
申请人： Allan Tanzman , Dennis J. W. Dube , Stephen Mooney
发明人： Allan Tanzman , Dennis J. W. Dube , Stephen Mooney
IPC分类号： G06F15/16 , G06F3/00 , G06F11/00 , G05B9/02
CPC分类号： G05B19/058 , G05B9/03 , G05B2219/14132
摘要： A method and apparatus for providing an active standby control system comprising the steps of providing a first and second programmable logic controller (PLC), each controller having an operating state. Each controller further including a network module board operably connected to a network; a control unit, a remote I/O head; and, a hot standby module, each hot standby module is operably connected together. Operably connecting each programmable logic controller to a network. Assigning a network address identifier, i.e., Internet Protocol or Media Access Control address, to each programmable logic controller and sensing the operating state of each programmable logic controller. The network address identifier of each programmable logic controller is determined by the operating state of each respective programmable logic controller. The present invention is also directed to an apparatus for communication with at least one device which resides on a standard communications network using a standard communications protocol. The apparatus has a scanner for scanning the device, a device scan table for storing data relating to the device, and a standard communications interface for interfacing between the device scanner and the standard communications network using the standard communication protocol.
摘要翻译：一种用于提供主动待机控制系统的方法和装置，包括以下步骤：提供第一和第二可编程逻辑控制器（PLC），每个控制器具有操作状态。每个控制器还包括可操作地连接到网络的网络模块板; 控制单元，远程I / O头; 和热备用模块，每个热备模块可操作地连接在一起。可操作地将每个可编程逻辑控制器连接到网络。向每个可编程逻辑控制器分配网络地址标识符，即因特网协议或媒体访问控制地址，并感测每个可编程逻辑控制器的操作状态。每个可编程逻辑控制器的网络地址标识符由每个可编程逻辑控制器的工作状态决定。本发明还涉及一种用于使用标准通信协议驻留在标准通信网络上的至少一个设备进行通信的装置。该装置具有用于扫描设备的扫描仪，用于存储与该设备有关的数据的设备扫描表以及用于使用标准通信协议在设备扫描器与标准通信网络之间进行接口的标准通信接口。

8. 发明申请

US20070064787A1 Adaptive equalization method and circuit for continuous run-time adaptation 有权
标题翻译：用于连续运行时适应的自适应均衡方法和电路
公开(公告)号：US20070064787A1
公开(公告)日：2007-03-22
申请号：US11232492
申请日：2005-09-21
申请人： James Jaussi , Bryan Casper , Ganesh Balamurugan , Stephen Mooney
发明人： James Jaussi , Bryan Casper , Ganesh Balamurugan , Stephen Mooney
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03057 , H04L2025/03598 , H04L2025/03681
摘要： In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.
摘要翻译：在本文公开的一些实施例中，接收机中的均衡器在正常操作期间被适配，因为它们从接收到的比特流中提取比特数据，以解决信道和/或电路波动。

9. 发明申请

US20050285667A1 Sign-sign least means square filter 有权
标题翻译：符号最小的意思是方形滤波器
公开(公告)号：US20050285667A1
公开(公告)日：2005-12-29
申请号：US10879417
申请日：2004-06-28
申请人： James Jaussi , Bryan Casper , Ganesh Balamuragan , Stephen Mooney
发明人： James Jaussi , Bryan Casper , Ganesh Balamuragan , Stephen Mooney
IPC分类号： H03B1/00 , H03H21/00
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

10. 发明申请

US20050070229A1 Receiver calibration apparatus, method, and system 有权
标题翻译：接收机校准装置，方法和系统
公开(公告)号：US20050070229A1
公开(公告)日：2005-03-31
申请号：US10674175
申请日：2003-09-29
申请人： Bryan Casper , Aaron Martin , James Jaussi , Stephen Mooney
发明人： Bryan Casper , Aaron Martin , James Jaussi , Stephen Mooney
IPC分类号： H04B17/00
CPC分类号： H04B17/21
摘要： A receiver is calibrated using a transmitter that can output a plurality of substantially constant amplitude signals.
摘要翻译：使用可以输出多个基本上恒定的振幅信号的发射机校准接收机。

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