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    • 4. 发明授权
    • Method of fabricating a parallel processor package
    • 制造并行处理器封装的方法
    • US5346117A
    • 1994-09-13
    • US97604
    • 1993-07-27
    • Harold KohnDonald J. Lazzarini
    • Harold KohnDonald J. Lazzarini
    • G06F13/40H05K1/00H05K3/00H05K3/32H05K3/40H05K3/46H05K3/36
    • H05K3/4635G06F13/409H05K3/462H05K1/0393H05K2201/0305H05K2201/0373H05K2201/09536H05K2201/09572H05K2201/096H05K2201/10159H05K3/328H05K3/4038H05K3/4623H05K3/4626H05K3/4641Y10T29/49126
    • Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.
    • 公开了一种用于制造堆叠电路化柔性结构的方法。 该结构是在并行处理器内用于Z轴通信的层压板。 该层压部分为处理器间,存储器间,处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 通过在单独的电路化柔性条中设置通孔和通孔来进行Z轴电路化。 这些通孔和通孔被循环和电镀。 然后在通孔和通孔的顶部和底部填充通孔和通孔用焊料和形成焊料凸块。 提供了具有用于焊料凸块的间隙孔的贴纸,并且堆叠多个电路化的柔性条以层压以形成电路化的柔性条的堆叠。 层压在升高的压力和温度下进行,以粉碎焊料凸块,粘合和均质焊料凸块材料并熔合贴纸。 接下来,将堆叠冷却以固化均质化的焊料凸块材料。