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1. 发明授权

US5717199A Collective charge reading and injection in random access charge transfer devices 失效
标题翻译：随机存取电荷转移装置中的集体电荷读取和注入
公开(公告)号：US5717199A
公开(公告)日：1998-02-10
申请号：US592789
申请日：1996-01-26
申请人： Joseph Carbone , M. Bonner Denton , Stephen W. Czebiniak , Jeffrey J. Zarnowski , Steven N. VanGorden , Michael J. Pilon
发明人： Joseph Carbone , M. Bonner Denton , Stephen W. Czebiniak , Jeffrey J. Zarnowski , Steven N. VanGorden , Michael J. Pilon
IPC分类号： H04N5/345 , H04N5/374 , H04N5/335
CPC分类号： H04N3/1518 , H04N3/1562
摘要： Random access charge transfer devices are provided in which it is possible to simultaneously read electric charge that is stored within each detection element (pixel) that is in one of any desired combination of columns and that is also in one of any desired combination of rows. It is also possible to simultaneously read electric charge stored within each detection element or pixel in at least one selected column or row. In addition, it is possible to simultaneously cause injection of some or all of the electric charge stored in each detection element in one of any desired combination of columns and also in one of any desired combination of rows, or to simultaneously cause injection of some or all of the electric charge stored in each detection element in at least one selected column or row. In certain embodiments, a plurality of pre-amplifiers are connected to the column or row electrodes of the charge transfer device, for simultaneously producing a plurality of outputs, each output corresponding to the electric charge stored within at least one detection element or pixel in a single column or row, and a summation amplifier is provided having a feedback loop that is connected into each of the pre-amplifiers.
摘要翻译：提供随机存取电荷转移装置，其中可以同时读取存储在任何期望的列组合之一中并且也处于任何期望的行组合之一的每个检测元件（像素）内的电荷。还可以同时读取存储在至少一个所选列或行中的每个检测元件或像素内的电荷。此外，可以同时引入存储在每个检测元件中的部分或全部电荷以任何期望的列组合之一并且还可以以任何期望的行组合之一注入，或者同时引起一些或多个存储在至少一个所选列或行中的每个检测元件中的所有电荷。在某些实施例中，多个预放大器连接到电荷转移装置的列或行电极，用于同时产生多个输出，每个输出对应于存储在至少一个检测元件或像素中的电荷提供单列或行，并且提供了具有连接到每个前置放大器中的反馈回路的求和放大器。

2. 发明授权

US07554067B2 Scanning imager employing multiple chips with staggered pixels 有权
标题翻译：扫描成像仪采用具有交错像素的多个芯片
公开(公告)号：US07554067B2
公开(公告)日：2009-06-30
申请号：US11589357
申请日：2006-10-30
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen , Li Liu
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen , Li Liu
IPC分类号： H01L27/00 , H04N3/14
CPC分类号： H04N5/2254 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H04N1/1911 , H04N1/1917 , H04N5/3692 , H04N9/045 , H04N2201/0081
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。位于微透镜阵列中，每个微透镜覆盖多个像素。每个微透镜下的不同像素可以沿对角线对齐。相同微透镜下的不同像素可以具有不同的积分时间，以增加成像器的动态范围。

3. 发明授权

US07122778B2 Scanning imager employing multiple chips with staggered pixels 有权
标题翻译：扫描成像仪采用具有交错像素的多个芯片
公开(公告)号：US07122778B2
公开(公告)日：2006-10-17
申请号：US11356199
申请日：2006-02-17
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00 , H04N3/14
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。

4. 发明申请

US20090231479A1 Image Sensor ADC and CDS per Column 有权
标题翻译：图像传感器ADC和CDS每列
公开(公告)号：US20090231479A1
公开(公告)日：2009-09-17
申请号：US12421948
申请日：2009-04-10
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
IPC分类号： H04N5/335
CPC分类号： H04N5/37455 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/35509 , H04N5/3575 , H04N5/361 , H04N5/365 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译：固态成像器将阵列每列的模拟像素值转换为数字形式。计数器耦合到N位DAC以产生对应于计数器的内容而变化的模拟斜坡。纹波计数器与每个相应的列相关联。在预定序列上的时钟或计数源向计数器元件提供时钟信号或计数。当模拟斜坡等于像素值时，列比较器将计数器元件选通。计数器内容供给视频输出总线以产生数字视频信号。附加的黑电平读出计数器元件可以创建并存储从像素值中减去的黑电平数字值以减少固定模式噪声。计数器可以使用二进制补码算术。可以采用附加的缓冲计数器/锁存器阵列。纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平时钟输出到输出总线。 DAC计数器和纹波计数器的时钟脉冲或计数可以是相同或不同的速率。

5. 发明授权

US07129461B2 Scanning imager employing multiple chips with staggered pixels 有权
标题翻译：扫描成像仪采用具有交错像素的多个芯片
公开(公告)号：US07129461B2
公开(公告)日：2006-10-31
申请号：US11434666
申请日：2006-05-16
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00 , H04N3/14
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。

6. 发明授权

US06194770B1 Photo receptor with reduced noise 失效
标题翻译：照片受体减少噪音
公开(公告)号：US06194770B1
公开(公告)日：2001-02-27
申请号：US09039833
申请日：1998-03-16
申请人： Jeffrey J. Zarnowski , Matthew A. Pace
发明人： Jeffrey J. Zarnowski , Matthew A. Pace
IPC分类号： H01L310232
CPC分类号： H01L27/14609 , H01L27/14603
摘要： An improved low voltage, small surface area, high signal-to-noise ratio photo gate includes a layer of photoreceptive semiconductor material having an impurity concentration selected to enhance the formation of hole electron pairs in response to photons impinging on a surface of the substrate, an electrode extending from the surface of the substrate into the substrate a substantial distance; an insulating layer disposed between the electrode and the substrate for electrically insulating the electrode from the substrate; so that upon the application of an electrical potential to the electrode, a potential well is formed in the substrate surrounding the electrode for accumulating charge generated when photons impinge on the surface of the substrate surrounding the electrode.
摘要翻译：改进的低电压，小表面积，高信噪比光栅包括具有选择的杂质浓度的光感受半导体材料层，以响应于撞击在衬底的表面上的光子而增强空穴电子对的形成，从衬底的表面延伸到衬底相当长的电极; 绝缘层，设置在所述电极和所述基板之间，用于将所述电极与所述基板电绝缘; 使得当对电极施加电位时，在围绕电极的基板中形成电位阱，用于当光子照射在围绕电极的基板的表面上时产生的电荷。

7. 发明授权

US07903159B2 Image sensor ADC and CDS per column 有权
标题翻译：图像传感器ADC和CDS每列
公开(公告)号：US07903159B2
公开(公告)日：2011-03-08
申请号：US12421948
申请日：2009-04-10
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/37455 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/35509 , H04N5/3575 , H04N5/361 , H04N5/365 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译：固态成像器将阵列每列的模拟像素值转换为数字形式。计数器耦合到N位DAC以产生对应于计数器的内容而变化的模拟斜坡。纹波计数器与每个相应的列相关联。在预定序列上的时钟或计数源向计数器元件提供时钟信号或计数。当模拟斜坡等于像素值时，列比较器将计数器元件选通。计数器内容供给视频输出总线以产生数字视频信号。附加的黑电平读出计数器元件可以创建并存储从像素值中减去的黑电平数字值以减少固定模式噪声。计数器可以使用二进制补码算术。可以采用附加的缓冲计数器/锁存器阵列。纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平时钟输出到输出总线。 DAC计数器和纹波计数器的时钟脉冲或计数可以是相同或不同的速率。

8. 发明授权

US07057150B2 Solid state imager with reduced number of transistors per pixel 失效
标题翻译：固态成像仪每像素数量减少
公开(公告)号：US07057150B2
公开(公告)日：2006-06-06
申请号：US10673591
申请日：2003-09-29
申请人： Jeffrey J. Zarnowski , Samuel D. Ambalavanar , Michael E. Joyner , Ketan V. Karia
发明人： Jeffrey J. Zarnowski , Samuel D. Ambalavanar , Michael E. Joyner , Ketan V. Karia
IPC分类号： H01J40/14
CPC分类号： H04N5/37457 , H01L27/14609 , H01L27/14641 , H04N5/335 , H04N5/347 , H04N5/363
摘要： A solid state imager with pixels arranged in columns and rows has the pixels are configured into groups of at least a first pixel and a second pixel, each said group sharing a pixel output transistor having a sense electrode and an output electrode and a reset transistor having a gate coupled to receive a reset signal and an output coupled to the sense electrode of the associated shared pixel output transistor. Each of the pixels has a photosensitive element whose output electrode is coupled to the sense electrode of the shared pixel output transistor and a gate electrode coupled to receive respective first and second pixel gating signals. This configuration reduces the number of FETs to two transistors for each pair of pixels, and also can achieve true correlated double sampling correction of FPN.
摘要翻译：具有排列成列和行的像素的固态成像器将像素配置成至少第一像素和第二像素的组，每个所述组共享具有感测电极和输出电极的像素输出晶体管，以及复位晶体管，其具有耦合以接收复位信号的栅极和耦合到相关联的共享像素输出晶体管的感测电极的输出。每个像素具有感光元件，其输出电极耦合到共享像素输出晶体管的感测电极，并且栅电极被耦合以接收相应的第一和第二像素门控信号。该配置将每对像素的FET数量减少到两个晶体管，并且还可以实现FPN的真实相关双采样校正。

9. 发明授权

US07045758B2 Scanning image employing multiple chips with staggered pixels 有权
标题翻译：使用具有交错像素的多个芯片的扫描图像
公开(公告)号：US07045758B2
公开(公告)日：2006-05-16
申请号：US11111334
申请日：2005-04-21
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00 , H04N3/14
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。

10. 发明授权

US6084229A Complimentary metal oxide semiconductor imaging device 失效
标题翻译：免费金属氧化物半导体成像装置
公开(公告)号：US6084229A
公开(公告)日：2000-07-04
申请号：US39835
申请日：1998-03-16
申请人： Matthew A. Pace , Jeffrey J. Zarnowski
发明人： Matthew A. Pace , Jeffrey J. Zarnowski
IPC分类号： H04N5/357 , H04N5/365 , H04N5/3745 , H04N5/378 , H01J40/14
CPC分类号： H04N5/3745 , H04N5/3575 , H04N5/3658 , H04N5/378
摘要： A CMOS imager includes a photosensitive device such as a photosensitive device such as a photodiode or photogate having a sense node coupled to an FET located adjacent to the photosensitive region. Another FET, forming a differential input pair of an operational amplifier is located outside of the array of pixels. The operational amplifier is configured for unity gain and a row or column of input FETs is connected in parallel. A correlated double sampler is connected to the output of the operational amplifier for providing a fixed pattern noise free signal.
摘要翻译： CMOS成像器包括诸如光敏器件的光敏器件，例如光电二极管或光栅，其具有耦合到位于光敏区附近的FET的感测节点。形成运算放大器的差分输入对的另一个FET位于像素阵列的外部。运算放大器配置为单位增益，并行输入FET的行或列并联。相关的双采样器连接到运算放大器的输出，用于提供固定模式无噪声信号。

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