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1. 发明授权

US06633938B1 Independent reset of arbiters and agents to allow for delayed agent reset 有权
标题翻译：仲裁人和代理人的独立复位以允许延迟代理重置
公开(公告)号：US06633938B1
公开(公告)日：2003-10-14
申请号：US09680525
申请日：2000-10-06
申请人： Joseph B. Rowlands , David L. Anderson , James Y. Cho
发明人： Joseph B. Rowlands , David L. Anderson , James Y. Cho
IPC分类号： G06F1200
CPC分类号： G06F13/368
摘要： A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.
摘要翻译：系统包括两个或多个代理和代理连接到的总线的分布式仲裁方案。因此，提供了对应于每个代理的仲裁器。使用第一复位信号复位仲裁器，同时使用单独的复位信号或信号复位代理。当第一复位信号被断言时，仲裁器同时从复位释放，并且可以具有一致的复位状态以提供仲裁器的同步。代理可以通过单独的复位信号独立地从复位释放。因此，仲裁者可以是同步的，并且即使相应的代理在不同的时间从复位中解除，或者由于任何原因暂时保持复位，可以保持同步。

2. 发明授权

US06865633B2 Independent reset of arbiters and agents to allow for delayed agent reset 有权
标题翻译：仲裁人和代理人的独立复位以允许延迟代理重置
公开(公告)号：US06865633B2
公开(公告)日：2005-03-08
申请号：US10640130
申请日：2003-08-13
申请人： Joseph B. Rowlands , David L. Anderson , James Y. Cho
发明人： Joseph B. Rowlands , David L. Anderson , James Y. Cho
IPC分类号： G06F12/00 , G06F13/00 , G06F13/368
CPC分类号： G06F13/368
摘要： A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.
摘要翻译：系统包括两个或多个代理和代理连接到的总线的分布式仲裁方案。因此，提供了对应于每个代理的仲裁器。使用第一复位信号复位仲裁器，同时使用单独的复位信号或信号复位代理。当第一复位信号被断言时，仲裁器同时从复位释放，并且可以具有一致的复位状态以提供仲裁器的同步。代理可以通过单独的复位信号独立地从复位释放。因此，仲裁者可以是同步的，并且即使相应的代理在不同的时间被从复位中解除，也可以保持同步，或者由于任何原因暂时保持复位。

3. 发明申请

US20100100681A1 System on a chip for networking 有权
公开(公告)号：US20100100681A1
公开(公告)日：2010-04-22
申请号：US12642736
申请日：2009-12-18
申请人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
发明人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
IPC分类号： G06F12/08
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

4. 发明授权

US07093052B2 Bus sampling on one edge of a clock signal and driving on another edge 失效
标题翻译：在一个时钟信号的一个边沿进行总线采样，并在另一个边沿驱动
公开(公告)号：US07093052B2
公开(公告)日：2006-08-15
申请号：US10715054
申请日：2003-11-17
申请人： James Y. Cho , Joseph B. Rowlands
发明人： James Y. Cho , Joseph B. Rowlands
IPC分类号： G06F13/14
CPC分类号： G06F13/423
摘要： An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal. By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive to the second edge. The sampled signals may be evaluated to determine an arbitration winner, which may drive the bus responsive to the next occurrence of the first edge.
摘要翻译：代理可以被耦合以接收与总线相关联的时钟信号，并且可以被配置为响应于时钟信号的第一边缘（上升或下降）和响应于第二边缘的采样信号来驱动信号。可以评估采样信号以允许在时钟信号的下一个出现的第一边沿上的信号的驱动。通过使用第一边沿来驱动信号并且第二边沿采样信号，专用于信号传播的时间量可以是一个半个时钟周期。带宽和/或延迟可能受到积极的影响。在一些实施例中，可以在更少的时钟周期内完成在其它总线上可能需要多个时钟周期的协议。例如，可能需要两个时钟周期的某些协议可以在一个时钟周期内完成。在一个具体实现中，例如，仲裁可以在一个时钟周期内完成。可以响应于时钟信号的第一边缘来响应于第二边沿进行采样的请求信号。可以评估采样的信号以确定仲裁胜利者，其可以响应于下一次出现第一边缘而驱动总线。

5. 发明授权

US07991922B2 System on a chip for networking 有权
标题翻译：系统在芯片上进行网络连接
公开(公告)号：US07991922B2
公开(公告)日：2011-08-02
申请号：US12642736
申请日：2009-12-18
申请人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
发明人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
摘要翻译：用于网络设备的芯片上的系统。在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

6. 发明申请

US20080276018A1 SYSTEM ON A CHIP FOR NETWORKING 有权
标题翻译：用于网络的芯片系统
公开(公告)号：US20080276018A1
公开(公告)日：2008-11-06
申请号：US12178101
申请日：2008-07-23
申请人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
发明人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
IPC分类号： G06F13/38
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
摘要翻译：用于网络设备的芯片上的系统。在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

7. 发明授权

US07418534B2 System on a chip for networking 有权
标题翻译：系统在芯片上进行网络连接
公开(公告)号：US07418534B2
公开(公告)日：2008-08-26
申请号：US10884700
申请日：2004-07-02
申请人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
发明人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
摘要翻译：用于网络设备的芯片上的系统。在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

8. 发明授权

US06816932B2 Bus precharge during a phase of a clock signal to eliminate idle clock cycle 失效
标题翻译：在一个时钟信号的相位期间，总线预充电以消除空闲时钟周期
公开(公告)号：US06816932B2
公开(公告)日：2004-11-09
申请号：US09858778
申请日：2001-05-15
申请人： James Y. Cho , Joseph B. Rowlands , Mark H. Pearce
发明人： James Y. Cho , Joseph B. Rowlands , Mark H. Pearce
IPC分类号： G06F1338
CPC分类号： G06F13/423 , G06F13/4077
摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

9. 发明授权

US07076582B2 Bus precharge during a phase of a clock signal to eliminate idle clock cycle 失效
公开(公告)号：US07076582B2
公开(公告)日：2006-07-11
申请号：US10950082
申请日：2004-09-24
申请人： James Y. Cho , Joseph B. Rowlands , Mark H. Pearce
发明人： James Y. Cho , Joseph B. Rowlands , Mark H. Pearce
IPC分类号： G06F13/38 , H03K19/00
CPC分类号： G06F13/423 , G06F13/4077
摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

10. 发明授权

US06766389B2 System on a chip for networking 有权
标题翻译：系统在芯片上进行网络连接
公开(公告)号：US06766389B2
公开(公告)日：2004-07-20
申请号：US09861191
申请日：2001-05-18
申请人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
发明人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
IPC分类号： G06F1300
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
摘要翻译：用于网络设备的芯片上的系统。在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

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