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1. 发明授权

US5388226A Method and apparatus for accessing a register in a data processing system 失效
标题翻译：用于访问数据处理系统中的寄存器的方法和装置
公开(公告)号：US5388226A
公开(公告)日：1995-02-07
申请号：US956194
申请日：1992-10-05
申请人： Joseph A. Gutierrez , William C. Moyer , Yui K. Ho , Pee-Keong Or
发明人： Joseph A. Gutierrez , William C. Moyer , Yui K. Ho , Pee-Keong Or
IPC分类号： G06F9/38 , G06F12/10 , G06F12/02
CPC分类号： G06F9/3834 , G06F12/1027 , G06F9/3824
摘要： A method and apparatus for accessing a register in a data processing system (10). In one form, the present invention uses a storage circuit (23) to act as a register copy (23) of the original register (33). An access to the register location may actually selectively access the original register (33), the register copy (23), or both the original register (33) and the register copy (23). Register select logic (70) is used to perform this selection function. Register select logic (70) may also be used to keep track of the current status of the contents of the original register (33) and of the contents of the register copy (23). Register select logic (70) may also monitor the internal state of data processing system (10).
摘要翻译：一种用于访问数据处理系统（10）中的寄存器的方法和装置。在一种形式中，本发明使用存储电路（23）作为原始寄存器（33）的寄存器复制（23）。访问寄存器位置实际上可以选择性地访问原始寄存器（33），寄存器复制件（23），或原始寄存器（33）和寄存器复制件（23）两者。寄存器选择逻辑（70）用于执行此选择功能。寄存器选择逻辑（70）也可用于跟踪原始寄存器（33）的内容和寄存器复制（23）的内容的当前状态。寄存器选择逻辑（70）也可以监视数据处理系统（10）的内部状态。

2. 发明授权

US5341500A Data processor with combined static and dynamic masking of operand for breakpoint operation 失效
标题翻译：具有组合静态和动态屏蔽操作数的数据处理器，用于断点操作
公开(公告)号：US5341500A
公开(公告)日：1994-08-23
申请号：US679478
申请日：1991-04-02
申请人： William C. Moyer , Joseph A. Gutierrez , Yui K. Ho
发明人： William C. Moyer , Joseph A. Gutierrez , Yui K. Ho
IPC分类号： G06F11/28 , G06F9/308 , G06F11/34
CPC分类号： G06F9/30018
摘要： A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20, 44, 48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).
摘要翻译：数据处理系统（10）实现断点地址的组合静态和动态屏蔽操作。静态掩码实现由用户指定的预定数量的比特的条件掩码，并且在存储在断点寄存器（24）中的断点地址与通过逻辑地址总线（11）传送的逻辑地址之间的比较操作之前确定，。动态掩码值实现一个可变掩码，允许数据处理系统根据断点地址访问的大小屏蔽断点地址。使用相同的电路组合静态屏蔽值和动态屏蔽值以形成组合屏蔽值（19）。断点功能和地址转换在系统（10）中通过使用相同的驱动和控制电路（20,44,48）实现这两个功能来实现。断点寄存器（24）被实现为CAM阵列（26）中的条目。

3. 发明授权

US5319763A Data processor with concurrent static and dynamic masking of operand information and method therefor 失效
标题翻译：数据处理器具有并发静态和动态屏蔽的操作数信息及其方法
公开(公告)号：US5319763A
公开(公告)日：1994-06-07
申请号：US679463
申请日：1991-04-02
申请人： Yui K. Ho , William C. Moyer , Joseph A. Gutierrez
发明人： Yui K. Ho , William C. Moyer , Joseph A. Gutierrez
IPC分类号： G06F7/00 , G06F7/76 , G06F9/308 , G06F11/28 , G06F15/82 , G06F9/22 , G06F9/26 , G06F11/18 , G06F13/30
CPC分类号： G06F9/30018
摘要： A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are concurrently implemented using a specialized bit cell (60) contained in both the breakpoint register (24) and the CAM array (26). The specialized bit cell (60) is comprised of two transistors (62 and 64) to concurrently mask a respective bit of operand information during a comparison operation.
摘要翻译：数据处理系统（10）同时实现操作数信息的静态和动态屏蔽操作。静态掩码实现由用户指定的预定数量的比特的条件掩码，并且在存储在断点寄存器（24）中的断点地址与通过逻辑地址总线（11）传送的逻辑地址之间的比较操作之前确定，。动态掩码值实现一个可变掩码，允许数据处理系统根据断点地址访问的大小屏蔽断点地址。使用包含在断点寄存器（24）和CAM阵列（26）中的专用位单元（60）同时实现静态掩码值和动态掩码值。专用位单元（60）由两个晶体管（62和64）组成，以在比较操作期间同时屏蔽操作数信息的相应位。

4. 发明授权

US5239642A Data processor with shared control and drive circuitry for both breakpoint and content addressable storage devices 失效
标题翻译：具有共享控制和驱动电路的数据处理器，用于断点和内容可寻址存储设备
公开(公告)号：US5239642A
公开(公告)日：1993-08-24
申请号：US679477
申请日：1991-04-02
申请人： Joseph A. Gutierrez , William C. Moyer , Yui K. Ho
发明人： Joseph A. Gutierrez , William C. Moyer , Yui K. Ho
IPC分类号： G06F11/34 , G06F11/36 , G06F12/10 , G11C11/00
CPC分类号： G06F11/362 , G06F11/3471 , G06F12/1027 , G11C11/005 , G06F2212/2515
摘要： A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20,44,48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).
摘要翻译：数据处理系统（10）实现断点地址的组合静态和动态屏蔽操作。静态掩码实现由用户指定的预定数量的比特的条件掩码，并且在存储在断点寄存器（24）中的断点地址与通过逻辑地址总线（11）传送的逻辑地址之间的比较操作之前确定，。动态掩码值实现一个可变掩码，允许数据处理系统根据断点地址访问的大小屏蔽断点地址。使用相同的电路组合静态屏蔽值和动态屏蔽值以形成组合屏蔽值（19）。断点功能和地址转换在系统（10）中通过使用相同的驱动和控制电路（20,44,48）实现这两个功能。断点寄存器（24）被实现为CAM阵列（26）中的条目。

5. 发明授权

US5732405A Method and apparatus for performing a cache operation in a data processing system 失效
标题翻译：用于在数据处理系统中执行高速缓存操作的方法和装置
公开(公告)号：US5732405A
公开(公告)日：1998-03-24
申请号：US336702
申请日：1994-11-08
申请人： Yui Kaye Ho , William C. Moyer , Joseph A. Gutierrez
发明人： Yui Kaye Ho , William C. Moyer , Joseph A. Gutierrez
IPC分类号： G06F12/10 , G06F12/04
CPC分类号： G06F12/1027
摘要： A method and apparatus for performing a cache operation in a data processing system (10). In one form, the present invention has a "block address translation cache (BATC) only mode" in which a received logical address is compared to the logical addresses stored in only one of a plurality of address translation caches, i.e. the block address translation cache (BATC) (76). The overhead associated with loading and comparing one or more other caches (78) is not incurred. If the comparison with that one cache (BATC) (76) produces a hit, that cache (BATC) (76) supplies the address that is used as the physical address. If the comparison with that one cache (BATC) (76) produces a miss, then a 1:1 mapping is used and the received logical address is used as the physical address.
摘要翻译：一种用于在数据处理系统（10）中执行高速缓存操作的方法和装置。在一种形式中，本发明具有“仅块模块地址转换高速缓存（BATC）模式”，其中接收到的逻辑地址与仅存储在多个地址转换高速缓存中的一个中的逻辑地址进行比较，即块地址转换高速缓存（BATC）（76）。与加载和比较一个或多个其他高速缓存（78）相关联的开销不被引起。如果与该一个缓存（BATC）（76）的比较产生命中，则该缓存（BATC）（76）提供用作物理地址的地址。如果与该一个缓存（BATC）（76）的比较产生未命中，则使用1：1映射，并将接收到的逻辑地址用作物理地址。

6. 发明授权

US07247807B2 Button having stiffer vertical motion and reduced lateral motion 失效
标题翻译：按钮具有更刚性的垂直运动和减少的横向运动
公开(公告)号：US07247807B2
公开(公告)日：2007-07-24
申请号：US10614141
申请日：2003-07-07
申请人： Joseph A. Gutierrez , William R. Haas
发明人： Joseph A. Gutierrez , William R. Haas
IPC分类号： H01H13/00 , H01H3/00
CPC分类号： H01H13/705 , H01H2221/016 , H01H2221/044 , H01H2233/004
摘要： One embodiment of the invention is a button for engaging an electrical switch comprising: a button post that transmits a vertical motion of the button to the electrical switch, an alignment post that registers against the electrical switch and reduces lateral motion of the button, and at least two runners that connect the button to a frame and includes reinforcement that stiffens the vertical motion of the button.
摘要翻译：本发明的一个实施例是用于接合电开关的按钮，包括：按钮柱，其将按钮的垂直运动传递到电开关;对准柱，其对着电开关进行注册并减小按钮的横向运动，并且在至少两个将按钮连接到框架的跑步者，并且包括加强按钮的垂直运动的加强件。

7. 发明授权

US5183267A Seal for sending unit 失效
标题翻译：密封发送单元
公开(公告)号：US5183267A
公开(公告)日：1993-02-02
申请号：US131107
申请日：1987-12-10
申请人： Yuri Ackerman , Joseph A. Gutierrez
发明人： Yuri Ackerman , Joseph A. Gutierrez
IPC分类号： G01F23/02 , F01M11/00 , F02F11/00 , F16B43/00 , F16J15/06 , F16J15/12 , G01F23/00
CPC分类号： F16J15/06 , F16B43/001 , F01M2011/0416
摘要： An oil seal unit for disposition between mating parts having opposed end face sealing surfaces. The seal unit has a casing with a radial flange having opposed end face surfaces and an inner margin portion. An elastomeric seal body with radially inner, outer and intermediate body portions is bonded to the casing. The seal body includes a radially space apart, continuous circular sealing ribs over lying each face of the casing; the seal body also has a radially inner portion defining an opening through which the shank portion of the mating part extends. The intermediate part of the seal body includes a collar element which deforms into snug fluid-tight sealing engagement within a recess defined in part by the seal and in part by portions of the mating parts.
摘要翻译：一种油封单元，用于配置具有相对的端面密封表面的配合部件之间。密封单元具有具有径向凸缘的壳体，该径向凸缘具有相对的端面表面和内边缘部分。具有径向内，外和中间体部分的弹性体密封体结合到壳体。密封体包括在壳体的每个表面上的径向间隔开的连续的圆形密封肋; 密封体还具有限定开口的径向内部，该配合部的柄部延伸穿过该开口。密封体的中间部分包括一个套环元件，该套环元件在部分由密封件和部分由配合部件的一部分限定的凹部内变形成紧密的流体密封密封接合。

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