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    • 2. 发明授权
    • Method to prevent leaving residual metal in CMP process of metal interconnect
    • 防止金属互连CMP工艺中留下残留金属的方法
    • US06599173B1
    • 2003-07-29
    • US09608941
    • 2000-06-30
    • Jose L. CruzCuc K. HuynhTimothy C. KrywanczykDouglas K. Sturtevant
    • Jose L. CruzCuc K. HuynhTimothy C. KrywanczykDouglas K. Sturtevant
    • B24B722
    • H01L21/3212Y02P80/30
    • A CMP slurry for and method of polishing a semiconductor wafer during formation of metal interconnects are disclosed. The present invention utilizes a first slurry comprising a first oxidizer, preferably ferric nitrate, to remove the excess metal of the metal interconnect but which leaves the metal residues on the surface of the wafer. A second slurry comprising another oxidizer, preferably potassium iodate solution, having a greater affinity to both the metal residue and the liner material than the underlying dielectric is used to remove the metal residue and liner material with significantly reduced scratching of the underlying dielectric. The more robust metal interconnects formed utilizing the present invention is effective in lowering the overall resistance of a wafer, reducing the number of shorts, and provides greater protection of the underlying dielectric. Overpolishing of the wafer and its associated problems are avoided.
    • 公开了一种用于在形成金属互连件期间研磨半导体晶片的CMP浆料和方法。 本发明利用包含第一氧化剂,优选硝酸铁的第一浆料来除去金属互连体的多余金属,但是留下晶片表面上的金属残留物。 使用包含另一种氧化剂(优选碘酸钾溶液)的第二种浆料,其比底层电介质对金属残余物和衬垫材料具有更大的亲和力,以便以显着减少的下面的电介质的刮擦去除金属残余物和衬垫材料。 利用本发明形成的更坚固的金属互连在降低晶片的整体电阻,减少短路数量方面是有效的,并且为下面的电介质提供更大的保护。 避免晶片的抛光及其相关问题。
    • 6. 发明申请
    • Method to etch chrome for photomask fabrication
    • 蚀刻铬用于光掩模制​​造的方法
    • US20080113275A1
    • 2008-05-15
    • US11559417
    • 2006-11-14
    • Shaun B. CrawfordThomas B. FaureCuc K. HuynhJames P. Levin
    • Shaun B. CrawfordThomas B. FaureCuc K. HuynhJames P. Levin
    • G03F1/00
    • G03F1/54G03F1/30G03F1/80
    • Methods for manufacturing a photomask, such as a chrome on glass photomask and a phase shift photomask are provided. A selective main chrome etch and a selective chrome overetch in the fabrication process provides a photomask having improved image quality and provides nominal image size control and image size uniformity across the photomask within current process flows and manufacturing steps. The selective etch process utilizes a main etch where the resist etch selectivity (amount of chrome removed to resist removed) is higher than in the overetch step in which the etch is more selective to removal of the resist layer relative to the chrome layer. To control the etch selectivities the composition of the etchant chemistry and/or the etchant reactor hardware settings (power, voltage, etc.) can be adjusted.
    • 提供了制造光掩模的方法,例如玻璃光掩模上的铬和相移光掩模。 选择性主铬蚀刻和制造工艺中的选择性铬过蚀刻提供了具有改进的图像质量的光掩模,并且在当前工艺流程和制造步骤中提供标称图像尺寸控制和光掩模上的图像尺寸均匀性。 选择性蚀刻工艺利用主蚀刻,其中抗蚀剂蚀刻选择性(去除的抗蚀剂去除量)比在蚀刻对于相对于铬层去除抗蚀剂层更有选择性的过蚀刻步骤中更高。 为了控制蚀刻选择性,可以调整蚀刻剂化学成分和/或蚀刻剂反应器硬件设置(功率,电压等)。
    • 8. 发明授权
    • Method for homogenizing device parameters through photoresist planarization
    • 通过光致抗蚀剂平坦化使器件参数均匀化的方法
    • US06387810B2
    • 2002-05-14
    • US09340796
    • 1999-06-28
    • Gary J. BeardsleyZhong X. HeCuc K. HuynhMichael P. McMahon
    • Gary J. BeardsleyZhong X. HeCuc K. HuynhMichael P. McMahon
    • H01L21304
    • H01L21/76224
    • In a fabrication process, photoresist is disposed over a semiconductor substrate (10), covering a front surface (11) of the substrate (10) and filling trenches (12, 14, 16, 18) therein. The photoresist is planarized in chemical mechanical polishing to achieve a uniform thickness throughout the substrate (10). An anisotropic etching process partially removes the photoresist in the trenches (12, 14, 16, 18), thereby creating recesses in the trenches (12, 14, 16, 18). Because the thickness of the photoresist is uniform throughout the substrate (10) before the etching process, the depths of the recesses in different trenches (12, 14, 16, 18) are substantially equal to each other. A uniform recess depth throughout the substrate (10) is thereby achieved. The uniform recess depth facilitates in ensuring the semiconductor devices fabricated on the substrate (10) to have consistent parameters, characteristics, and performances.
    • 在制造工艺中,将光致抗蚀剂设置在半导体衬底(10)上,覆盖衬底(10)的前表面(11)并在其中填充沟槽(12,14,16,18)。 光致抗蚀剂在化学机械抛光中被平坦化,以在整个基底(10)上实现均匀的厚度。 各向异性蚀刻工艺部分去除沟槽(12,14,16,18)中的光致抗蚀剂,从而在沟槽(12,14,16,18)中产生凹陷。 由于在蚀刻工艺之前,光致抗蚀剂的厚度在整个基板(10)上是均匀的,所以不同沟槽(12,14,16,18)中的凹槽的深度基本相等。 从而实现整个基板(10)的均匀凹陷深度。 均匀凹陷深度有助于确保制造在基板(10)上的半导体器件具有一致的参数,特性和性能。