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    • 5. 发明授权
    • Method for fabricating polycide dual gate in semiconductor device
    • 在半导体器件中制造多晶硅双栅极的方法
    • US06528401B2
    • 2003-03-04
    • US09735544
    • 2000-12-14
    • Jong Uk BaeJi Soo ParkDong Kyun Sohn
    • Jong Uk BaeJi Soo ParkDong Kyun Sohn
    • H01L214763
    • H01L21/823842H01L21/823835
    • Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.
    • 在半导体器件中制造多晶硅双栅极的方法制造具有多晶硅栅极电极的双栅极。 例如,多硅化物可以是多硅化钴。 该方法可以包括在半导体衬底的第一和第二区域上形成多晶硅图案层,形成阻挡层以暴露多晶硅图案层的顶表面并掩蔽衬底,并在整个表面上形成金属层,然后是 退火以形成在硅化物层下方具有多晶硅图案层的堆叠的栅电极。 第一和第二区域中相反电导率的杂质离子可以分别沉积并扩散,以在栅电极两侧的衬底表面形成源/漏区。 注入的杂质离子可以在硅化物/多晶硅图案层栅极中进一步注入离子以减少制造步骤或简化制造工艺。
    • 8. 发明授权
    • Semiconductor device and method for fabricating same
    • 半导体装置及其制造方法
    • US06455404B1
    • 2002-09-24
    • US09710840
    • 2000-11-14
    • Jong Uk BaeJi Soo ParkBong Soo Kim
    • Jong Uk BaeJi Soo ParkBong Soo Kim
    • H01L213205
    • H01L29/66583H01L21/28114H01L29/66553
    • A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconductor substrate; a first insulating spacer formed at both sides above the gate electrode; a second insulating spacer formed at both sides below the gate electrode; and a cobalt silicide film formed on a surface of the gate electrode at a predetermined depth. The method for fabricating the semiconductor device includes the steps of: forming a first insulating film having a hole to expose a part of a semiconductor substrate; forming a second insulating film on the exposed semiconductor substrate inside the hole; forming a gate electrode on the second insulating film to protrude more than the first insulating film; forming a first insulating spacer at both sides of an upper part of the protruded gate electrode; forming a cobalt silicide on a surface of the upper part of the gate electrode; and selectively removing the first insulating film to remain on both sides of a lower part of the gate electrode, so that a second insulating spacer is formed.
    • 公开了一种提高半导体器件的可靠性的半导体器件及其制造方法。 半导体器件包括:第一绝缘膜和顺序地形成在半导体衬底的一部分上的栅电极; 形成在栅电极上方的两侧的第一绝缘间隔物; 形成在栅电极下方的两侧的第二绝缘间隔物; 以及在预定深度处形成在栅电极的表面上的钴硅化物膜。 制造半导体器件的方法包括以下步骤:形成具有孔的第一绝缘膜以暴露半导体衬底的一部分; 在所述孔内的所述暴露的半导体衬底上形成第二绝缘膜; 在所述第二绝缘膜上形成栅电极以使所述第一绝缘膜突出; 在突出栅电极的上部的两侧形成第一绝缘间隔物; 在所述栅电极的上部表面上形成硅化钴; 并且选择性地去除第一绝缘膜以保留在栅电极的下部的两侧,从而形成第二绝缘间隔物。
    • 9. 发明授权
    • Method for fabricating semiconductor device
    • 制造半导体器件的方法
    • US06342441B1
    • 2002-01-29
    • US09434520
    • 1999-11-05
    • Ji Soo ParkDong Kyun Son
    • Ji Soo ParkDong Kyun Son
    • H01L2122
    • H01L21/2257H01L21/2652H01L21/28518H01L21/3215H01L29/665H01L29/66575
    • A method for fabricating a semiconductor substrate includes forming a silicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.
    • 一种制造半导体衬底的方法包括在半导体衬底的预定部分形成硅化物层,在退火之前注入两种或更多种杂质离子,以及通过退火硅化物层并通过扩散杂质离子在半导体衬底中形成杂质区 从硅化物层进入半导体衬底。 因此,本发明可以通过减少衬底中PN结的掺杂剂损耗和漏电流以及降低硅化物层的薄层电阻来提高半导体器件的可靠性和性能。 第二注入离子的剂量比第一注入离子的剂量小约一百到一千倍。