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1. 发明授权

US08471643B2 Electromechanical systems oscillator with piezoelectric contour mode resonator for multiple frequency generation 失效
标题翻译：具有压电轮廓模式谐振器的机电系统振荡器用于多频发生
公开(公告)号：US08471643B2
公开(公告)日：2013-06-25
申请号：US13107764
申请日：2011-05-13
申请人： Jonghae Kim , Je-Hsiung Lan , Changhan Yun , Chi Shun Lo , Matthew Nowak
发明人： Jonghae Kim , Je-Hsiung Lan , Changhan Yun , Chi Shun Lo , Matthew Nowak
IPC分类号： H03B5/30
CPC分类号： H03H9/2426 , H03H9/02228 , H03H9/2405 , H03H9/462 , H03H2009/241
摘要： Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications.
摘要翻译：公开了机电系统谐振器结构，器件，电路和系统。一方面，振荡器包括以反馈配置连接的有源部件和无源部件。无源部件包括一个或多个轮廓模式谐振器（CMR）。 CMR包括设置在第一导电层和第二导电层之间的压电层。导电层包括输入电极和输出电极。无源部件被配置为输出第一谐振频率和第二谐振频率，其是第一谐振频率的奇整数谐波。有源部件被配置为输出包括第一谐振频率和第二谐振频率的信号。该输出信号可以是基本上为方波信号，其可以用作各种应用中的时钟。

2. 发明申请

US20120286886A1 Electromechanical Systems Oscillator with Piezoelectric Contour Mode Resonator for Multiple Frequency Generation 失效
标题翻译：机电系统振荡器用于多频发生的压电轮廓模式谐振器
公开(公告)号：US20120286886A1
公开(公告)日：2012-11-15
申请号：US13107764
申请日：2011-05-13
申请人： Jonghae Kim , Je-Hsiung Lan , Changhan Yun , Chi Shun Lo , Matthew Nowak
发明人： Jonghae Kim , Je-Hsiung Lan , Changhan Yun , Chi Shun Lo , Matthew Nowak
IPC分类号： H03B7/14
CPC分类号： H03H9/2426 , H03H9/02228 , H03H9/2405 , H03H9/462 , H03H2009/241
摘要： Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications.
摘要翻译：公开了机电系统谐振器结构，器件，电路和系统。一方面，振荡器包括以反馈配置连接的有源部件和无源部件。无源部件包括一个或多个轮廓模式谐振器（CMR）。 CMR包括设置在第一导电层和第二导电层之间的压电层。导电层包括输入电极和输出电极。无源部件被配置为输出第一谐振频率和第二谐振频率，其是第一谐振频率的奇整数谐波。有源部件被配置为输出包括第一谐振频率和第二谐振频率的信号。该输出信号可以是基本上为方波信号，其可以用作各种应用中的时钟。

3. 发明申请

US20120293520A1 PIEZOELECTRIC RESONATORS WITH CONFIGURATIONS HAVING NO GROUND CONNECTIONS TO ENHANCE ELECTROMECHANICAL COUPLING 审中-公开
标题翻译：具有无接地连接的配置的压电谐振器，以增强机电耦合
公开(公告)号：US20120293520A1
公开(公告)日：2012-11-22
申请号：US13111683
申请日：2011-05-19
申请人： Changhan Yun , Sang-June Park , Chi Shun Lo , Jonghae Kim , Je-Hsiung Lan , Sanghoon Joo
发明人： Changhan Yun , Sang-June Park , Chi Shun Lo , Jonghae Kim , Je-Hsiung Lan , Sanghoon Joo
IPC分类号： G06T1/00 , H03H9/17
CPC分类号： H03H9/173 , H03H9/02228
摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, resonator apparatus includes a first conductive layer including a first electrode and a second electrode. The first electrode is coupled to receive a first input signal, and the second electrode is coupled to provide a first output signal. A piezoelectric layer includes a piezoelectric material. The piezoelectric layer has a first side and a second side opposite the first side. The first side is proximate the first conductive layer, and the second side is electrically isolated from ground. In some examples, the second side of the piezoelectric layer can be exposed and/or electrically de-coupled from one or more components.
摘要翻译：本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。在一个方面，谐振器装置包括包括第一电极和第二电极的第一导电层。第一电极被耦合以接收第一输入信号，并且第二电极被耦合以提供第一输出信号。压电层包括压电材料。压电层具有与第一侧相对的第一侧和第二侧。第一侧靠近第一导电层，第二侧与地电隔离。在一些示例中，压电层的第二面可以暴露和/或从一个或多个部件电脱耦合。

4. 发明授权

US08093982B2 Three dimensional inductor and transformer design methodology of glass technology 有权
标题翻译：玻璃技术的三维电感和变压器设计方法
公开(公告)号：US08093982B2
公开(公告)日：2012-01-10
申请号：US12731393
申请日：2010-03-25
申请人： Jonghae Kim , Milind P. Shah , Chi Shun Lo , Je-Hsiung Lan , Xia Li , Matthew Michael Nowak
发明人： Jonghae Kim , Milind P. Shah , Chi Shun Lo , Je-Hsiung Lan , Xia Li , Matthew Michael Nowak
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F2017/004 , H01L21/84 , H01L23/645 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.
摘要翻译：一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。电感器包括围绕衬底的多个导电迹线，形成从第一端口到第二端口的连续导电路径。导电路径可以是螺线管形的。一些导电迹线可以在集成电路管芯的后端处理或背面电镀期间形成。变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。第二电感器与第一电感器无关并与其电磁耦合。第一和第二导电路径可以是螺线管形的。第一导电路径可以与第二导电路径交错。

5. 发明申请

US20110234357A1 Three Dimensional Inductor and Transformer Design Methodology of Glass Technology 有权
标题翻译：玻璃技术三维电感和变压器设计方法
公开(公告)号：US20110234357A1
公开(公告)日：2011-09-29
申请号：US12731393
申请日：2010-03-25
申请人： Jonghae Kim , Milind P. Shah , Chi Shun Lo , Je-Hsiung Lan , Xia Li , Matthew Michael Nowak
发明人： Jonghae Kim , Milind P. Shah , Chi Shun Lo , Je-Hsiung Lan , Xia Li , Matthew Michael Nowak
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F2017/004 , H01L21/84 , H01L23/645 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.
摘要翻译：一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。电感器包括围绕衬底的多个导电迹线，形成从第一端口到第二端口的连续导电路径。导电路径可以是螺线管形的。一些导电迹线可以在集成电路管芯的后端处理或背面电镀期间形成。变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。第二电感器与第一电感器无关并与其电磁耦合。第一和第二导电路径可以是螺线管形的。第一导电路径可以与第二导电路径交错。

6. 发明授权

US09008602B2 Radio frequency switch for diversity receiver 有权
标题翻译：用于分集接收机的射频开关
公开(公告)号：US09008602B2
公开(公告)日：2015-04-14
申请号：US13464092
申请日：2012-05-04
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H04B1/06 , H04B1/44 , H03C7/02 , H01Q11/12 , H04M1/00 , H04B1/16 , H04B1/00 , H04B7/08
CPC分类号： H04B7/0805 , H04B1/005 , H04B1/16 , H04B1/18 , H04B7/0825
摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
摘要翻译：分集接收机交换机包括被配置为与收发机通信的至少一个第二级交换机。分集接收机交换机还可以包括耦合在分集接收机天线和第二级交换机之间的至少一个第一级交换机。第一级开关可以被配置为处理与第二级开关不同的功率量。分集接收器开关可以包括被配置为与收发器通信的一组第二级交换机。第一级开关可以被配置为处理比第二级开关组中的每个开关更多的功率。或者，分集接收器开关包括耦合在分集接收器天线和第二级开关之间的一组第一级开关。第二级开关可以被配置为处理比每个第一级开关更多的功率。

7. 发明授权

US08907450B2 Metal-semiconductor wafer bonding for high-Q devices 有权
标题翻译：用于高Q器件的金属半导体晶片接合
公开(公告)号：US08907450B2
公开(公告)日：2014-12-09
申请号：US13293075
申请日：2011-11-09
申请人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
IPC分类号： H01L29/92 , H01L21/02 , H01G4/12 , H01G4/33 , H01L49/02
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
摘要翻译：提供了用于高Q装置的金属半导体晶片接合的方法和装置。示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。重掺杂的非本征半导体层接触电介质层。电介质和非本征半导体层夹在第一和第二板之间。在第一板和电介质层之间形成金属间层。金属间化合物层被热压接合到第一板和电介质层。电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

8. 发明申请

US20130295866A1 RADIO FREQUENCY SWITCH FOR DIVERSITY RECEIVER 有权
公开(公告)号：US20130295866A1
公开(公告)日：2013-11-07
申请号：US13464092
申请日：2012-05-04
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H04B1/16
CPC分类号： H04B7/0805 , H04B1/005 , H04B1/16 , H04B1/18 , H04B7/0825
摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

9. 发明申请

US20130222060A1 MUTUALLY COUPLED MATCHING NETWORK 审中-公开
标题翻译： MUTUALLY耦合匹配网络
公开(公告)号：US20130222060A1
公开(公告)日：2013-08-29
申请号：US13406431
申请日：2012-02-27
申请人： Chi Shun Lo , Jonghae Kim , Wesley Nathaniel Allen , Chengjie Zuo , Changhan Yun , Thomas Andrew Myers , Prasad Srinivasa Siva Gudem , Matthew Michael Nowak
发明人： Chi Shun Lo , Jonghae Kim , Wesley Nathaniel Allen , Chengjie Zuo , Changhan Yun , Thomas Andrew Myers , Prasad Srinivasa Siva Gudem , Matthew Michael Nowak
IPC分类号： H03H7/38 , H03F1/00
CPC分类号： H03H7/38 , H03H7/09
摘要： An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.
摘要翻译：公开了一种阻抗匹配电路。阻抗匹配电路包括两个或更多个相互耦合的电感器。阻抗匹配电路的总自感小于包括不相互耦合的电感器的对应阻抗匹配电路。两个或更多个相互耦合的电感器可以具有与相应的阻抗匹配电路中的电流比匹配的已知电流比。

10. 发明申请

US20130120951A1 STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME 有权
标题翻译：具有绝缘层和二次层的堆叠CMOS芯片及其形成方法
公开(公告)号：US20130120951A1
公开(公告)日：2013-05-16
申请号：US13356717
申请日：2012-01-24
申请人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H05K1/03 , H01L21/60 , H05K7/06 , H01L21/58
CPC分类号： H01L27/0688 , H01L2224/18
摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
摘要翻译：芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。还有一种形成芯片组的方法。

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