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1. 发明申请

US20110256708A1 Methods of Manufacturing Flash Memory Devices by Selective Removal of Nitrogen Atoms 有权
标题翻译：通过选择性去除氮原子制造闪存器件的方法
公开(公告)号：US20110256708A1
公开(公告)日：2011-10-20
申请号：US13085631
申请日：2011-04-13
申请人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
发明人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
IPC分类号： H01L21/321 , H01L21/283
CPC分类号： H01L21/3105 , H01L21/76826 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.
摘要翻译：制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

2. 发明授权

US08492223B2 Methods of manufacturing flash memory devices by selective removal of nitrogen atoms 有权
标题翻译：通过选择性去除氮原子来制造闪存器件的方法
公开(公告)号：US08492223B2
公开(公告)日：2013-07-23
申请号：US13085631
申请日：2011-04-13
申请人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
发明人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
IPC分类号： H01L21/321
CPC分类号： H01L21/3105 , H01L21/76826 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.
摘要翻译：制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

3. 发明授权

US08043914B2 Methods of fabricating flash memory devices comprising forming a silicide on exposed upper and side surfaces of a control gate 有权
标题翻译：制造闪存器件的方法包括在暴露的控制栅极的上表面和侧表面上形成硅化物
公开(公告)号：US08043914B2
公开(公告)日：2011-10-25
申请号：US12629920
申请日：2009-12-03
申请人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
发明人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.
摘要翻译：提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间与多个单元栅极线相对的线。在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。可以在形成间隔物的空间中形成第二绝缘层。

4. 发明申请

US20100167490A1 Method of Fabricating Flash Memory Device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US20100167490A1
公开(公告)日：2010-07-01
申请号：US12629920
申请日：2009-12-03
申请人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
发明人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.
摘要翻译：提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间与多个单元栅极线相对的线。在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。可以在形成间隔物的空间中形成第二绝缘层。

5. 发明授权

US08536652B2 Non-volatile memory devices including low-K dielectric gaps in substrates 有权
标题翻译：非易失性存储器件，包括衬底中的低K电介质间隙
公开(公告)号：US08536652B2
公开(公告)日：2013-09-17
申请号：US13224427
申请日：2011-09-02
申请人： Bo-young Lee , Jong-wan Choi , Jin-gi Hong , Myoung-bum Lee
发明人： Bo-young Lee , Jong-wan Choi , Jin-gi Hong , Myoung-bum Lee
IPC分类号： H01L29/78
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11568
摘要： A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.
摘要翻译：可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

6. 发明申请

US20120061763A1 METHODS OF FORMING NON-VOLATILE MEMORY DEVICES INCLUDING LOW-K DIELECTRIC GAPS IN SUBSTRATES AND DEVICES SO FORMED 有权
标题翻译：形成非易失性存储器件的方法，包括底片中的低K电介质GAPS和形成的器件
公开(公告)号：US20120061763A1
公开(公告)日：2012-03-15
申请号：US13224427
申请日：2011-09-02
申请人： Bo-young LEE , Jong-wan Choi , Jin-gi Hong , Myoung-bum Lee
发明人： Bo-young LEE , Jong-wan Choi , Jin-gi Hong , Myoung-bum Lee
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11568
摘要： A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.
摘要翻译：可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

7. 发明申请

US20080206954A1 METHODS OF REDUCING IMPURITY CONCENTRATION IN ISOLATING FILMS IN SEMICONDUCTOR DEVICES 有权
标题翻译：降低半导体器件隔离膜中污染浓度的方法
公开(公告)号：US20080206954A1
公开(公告)日：2008-08-28
申请号：US12038278
申请日：2008-02-27
申请人： Jong-wan Choi , Eun-kyung Baek , Sang-hoon Ahn , Hong-gun Kim , Dong-chul Suh , Yong-soon Choi
发明人： Jong-wan Choi , Eun-kyung Baek , Sang-hoon Ahn , Hong-gun Kim , Dong-chul Suh , Yong-soon Choi
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.
摘要翻译：制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。上沟槽形成在上半导体衬底内。上部器件隔离膜形成在上部沟槽内。用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

8. 发明授权

US07867924B2 Methods of reducing impurity concentration in isolating films in semiconductor devices 有权
标题翻译：降低半导体器件隔离膜杂质浓度的方法
公开(公告)号：US07867924B2
公开(公告)日：2011-01-11
申请号：US12038278
申请日：2008-02-27
申请人： Jong-wan Choi , Eun-kyung Baek , Sang-hoon Ahn , Hong-gun Kim , Dong-chul Suh , Yong-soon Choi
发明人： Jong-wan Choi , Eun-kyung Baek , Sang-hoon Ahn , Hong-gun Kim , Dong-chul Suh , Yong-soon Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.
摘要翻译：制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。上沟槽形成在上半导体衬底内。上部器件隔离膜形成在上部沟槽内。用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

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