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1. 发明申请

US20110103166A1 LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于半导体存储器件的位线感测放大器的布局结构
公开(公告)号：US20110103166A1
公开(公告)日：2011-05-05
申请号：US12987539
申请日：2011-01-10
申请人： YOUNG-SUN MIN , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
发明人： YOUNG-SUN MIN , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
IPC分类号： G11C7/06 , H03F3/68 , H03F3/16 , G06F17/50
CPC分类号： G11C7/18 , G11C5/025 , G11C7/065 , G11C2207/002
摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
摘要翻译：用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

2. 发明授权

US07869239B2 Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
标题翻译：用于半导体存储器件的位线读出放大器的布局结构
公开(公告)号：US07869239B2
公开(公告)日：2011-01-11
申请号：US12078724
申请日：2008-04-03
申请人： Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
发明人： Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
IPC分类号： G11C5/02
CPC分类号： G11C7/18 , G11C5/025 , G11C7/065 , G11C2207/002
摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
摘要翻译：用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

3. 发明授权

US07298655B2 Isolation control circuit and method for a memory device 有权
标题翻译：用于存储器件的隔离控制电路和方法
公开(公告)号：US07298655B2
公开(公告)日：2007-11-20
申请号：US11073765
申请日：2005-03-08
申请人： Jong-Hyun Choi , Young-Sun Min
发明人： Jong-Hyun Choi , Young-Sun Min
IPC分类号： G11C16/04
CPC分类号： G11C11/4091 , G11C11/4094 , G11C2207/005
摘要： A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.
摘要翻译：半导体存储器包括存储单元阵列，读出放大器，插入在读出放大器和存储单元阵列的位线之间的隔离装置，以及用于将包含在存储单元阵列的存储单元中的电荷传送到位线而隔离装置将位线与读出放大器电隔离，并且在电荷被传送到位线之后，用于使隔离装置将位线电连接到读出放大器。

4. 发明授权

US07259978B2 Semiconductor memory devices and signal line arrangements and related methods 失效
标题翻译：半导体存储器件和信号线布置及相关方法
公开(公告)号：US07259978B2
公开(公告)日：2007-08-21
申请号：US11221684
申请日：2005-09-08
申请人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
发明人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14
摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.
摘要翻译：半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。位线读出放大器可以被配置为感测和放大位线对的数据。子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。还讨论了信号线布置的相关方法。

5. 发明申请

US20080259668A1 Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
标题翻译：用于半导体存储器件的位线读出放大器的布局结构
公开(公告)号：US20080259668A1
公开(公告)日：2008-10-23
申请号：US12078724
申请日：2008-04-03
申请人： Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
发明人： Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
IPC分类号： G11C5/02 , G11C7/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/065 , G11C2207/002
摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
摘要翻译：用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

6. 发明授权

US07330384B2 Verifying circuit and method of repairing semiconductor device 有权
标题翻译：验证电路和修复半导体器件的方法
公开(公告)号：US07330384B2
公开(公告)日：2008-02-12
申请号：US11261497
申请日：2005-10-31
申请人： Young-Sun Min , Jong-Hyun Choi , Nam-Jong Kim
发明人： Young-Sun Min , Jong-Hyun Choi , Nam-Jong Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/787 , G11C17/18
摘要： A verifying circuit and a method of repairing a semiconductor device, the verifying circuit of example embodiments may include a first fuse circuit configured to determine whether a first fuse has been programmed, a test signal generating circuit configured to generate a test signal based on a control signal and an output signal from the first fuse circuit, and a second fuse circuit configured to test whether a plurality of second fuses are programmed based on the test signal.
摘要翻译：一种验证电路和修复半导体器件的方法，示例实施例的验证电路可以包括配置为确定第一熔丝是否已被编程的第一熔丝电路，被配置为基于控制产生测试信号的测试信号产生电路信号和来自第一熔丝电路的输出信号，以及第二熔丝电路，被配置为基于测试信号测试多个第二熔丝是否被编程。

7. 发明授权

US07349278B2 DRAM and method for partially refreshing memory cell array 有权
标题翻译：用于部分刷新存储单元阵列的DRAM和方法
公开(公告)号：US07349278B2
公开(公告)日：2008-03-25
申请号：US11485565
申请日：2006-07-12
申请人： Young-Sun Min , Jong-Hyun Choi , Nam-Jong Kim
发明人： Young-Sun Min , Jong-Hyun Choi , Nam-Jong Kim
IPC分类号： G11C29/00
CPC分类号： G11C11/406 , G11C11/40622
摘要： A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first refresh period of the PASR mode; and concurrently refreshing the first and second single cells that are included in the twin cell, during subsequent refresh periods of the PASR mode following the first refresh period. Embodiments according to the invention can extend the period of refresh operations by applying a PASR technique for a twin cell to a single cell and thereby reduce the power consumption of the refresh operations.
摘要翻译：用于动态随机存取存储器（DRAM）设备的部分阵列自刷新（PASR）操作的方法包括启动PASR模式; 在PASR模式的第一刷新周期期间将数据写入双胞胎单元的第一单个单元并将数据反转为双胞胎单元的第二单元; 并且在第一刷新周期之后的PASR模式的后续刷新周期期间同时刷新包含在双胞胎单元中的第一和第二单个单元。根据本发明的实施例可以通过将双胞胎的PASR技术应用于单个小区来延长刷新操作的周期，从而降低刷新操作的功耗。

8. 发明申请

US20060007753A1 Isolation control circuit and method for a memory device 有权
标题翻译：用于存储器件的隔离控制电路和方法
公开(公告)号：US20060007753A1
公开(公告)日：2006-01-12
申请号：US11073765
申请日：2005-03-08
申请人： Jong-Hyun Choi , Young-Sun Min
发明人： Jong-Hyun Choi , Young-Sun Min
IPC分类号： G11C7/10
CPC分类号： G11C11/4091 , G11C11/4094 , G11C2207/005
摘要： A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.
摘要翻译：半导体存储器包括存储单元阵列，读出放大器，插入在读出放大器和存储单元阵列的位线之间的隔离装置，以及用于将包含在存储单元阵列的存储单元中的电荷传送到位线而隔离装置将位线与读出放大器电隔离，并且在电荷被传送到位线之后，用于使隔离装置将位线电连接到读出放大器。

9. 发明授权

US08310853B2 Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
标题翻译：用于半导体存储器件的位线读出放大器的布局结构
公开(公告)号：US08310853B2
公开(公告)日：2012-11-13
申请号：US12987539
申请日：2011-01-10
申请人： Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
发明人： Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
IPC分类号： G11C5/02
CPC分类号： G11C7/18 , G11C5/025 , G11C7/065 , G11C2207/002
摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
摘要翻译：用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

10. 发明申请

US20070133320A1 Circuit and method of boosting voltage for a semiconductor memory device 审中-公开
标题翻译：用于半导体存储器件的升压电压的电路和方法
公开(公告)号：US20070133320A1
公开(公告)日：2007-06-14
申请号：US11634599
申请日：2006-12-06
申请人： Young-Sun Min , Jong-Hyun Choi
发明人： Young-Sun Min , Jong-Hyun Choi
IPC分类号： G11C7/00
CPC分类号： G11C5/145
摘要： A voltage boosting circuit of a semiconductor memory device for decreasing power consumption can include a first precharge circuit, a second precharge circuit, a first capacitive element, a second capacitive element and a coupling circuit. The first precharge circuit precharges a first node using a first supply voltage and the second precharge circuit precharges a second node using a second supply voltage. The first capacitive element boosts a voltage level of the first node in response to a first pulse signal and the second capacitive element boosts a voltage level of the second node in response to a second pulse signal. The coupling circuit electrically couples the first node to the second node in response to a boosting enable signal and a self-refresh control signal.
摘要翻译：用于降低功耗的半导体存储器件的升压电路可以包括第一预充电电路，第二预充电电路，第一电容元件，第二电容元件和耦合电路。第一预充电电路使用第一电源电压对第一节点进行预充电，并且第二预充电电路使用第二电源电压预充电第二节点。第一电容元件响应于第一脉冲信号而升高第一节点的电压电平，并且第二电容元件响应于第二脉冲信号而升高第二节点的电压电平。响应于升压使能信号和自刷新控制信号，耦合电路将第一节点电耦合到第二节点。

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