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1. 发明申请

US20100118615A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20100118615A1
公开(公告)日：2010-05-13
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C7/12 , G11C7/10
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

2. 发明申请

US20100259963A1 Data line layouts 有权
标题翻译：数据线布局
公开(公告)号：US20100259963A1
公开(公告)日：2010-10-14
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

3. 发明授权

US08547766B2 Area-efficient data line layouts to suppress the degradation of electrical characteristics 有权
标题翻译：区域高效的数据线布局，以抑制电气特性的恶化
公开(公告)号：US08547766B2
公开(公告)日：2013-10-01
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

4. 发明授权

US08130577B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08130577B2
公开(公告)日：2012-03-06
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

5. 发明授权

US06522564B2 Semiconductor memory device and signal line arrangement method thereof 有权
公开(公告)号：US06522564B2
公开(公告)日：2003-02-18
申请号：US10004558
申请日：2001-12-03
申请人： Jong-Hak Won
发明人： Jong-Hak Won
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： The present invention discloses a semiconductor memory device and a method of signal line arrangement. The semiconductor memory device comprises a plurality of memory cell array blocks, a number of pairs of local data input/output lines arranged along a longitudinal direction in each of the memory cell array blocks, multiple column selecting signal lines arranged along an orthogonal direction, and a number of twisted pairs of global data input/output lines arranged adjacent to and along the same direction as the column selecting signal line. Therefore, reducing signal coupling among the column selecting signal line and the pair of global data input/output lines.

6. 发明授权

US5798969A Data output buffer control circuit of a synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件的数据输出缓冲器控制电路
公开(公告)号：US5798969A
公开(公告)日：1998-08-25
申请号：US770784
申请日：1996-12-20
申请人： Hak-Soo Yoo , Jong-Hak Won
发明人： Hak-Soo Yoo , Jong-Hak Won
IPC分类号： G11C11/417 , G11C7/10 , G11C11/407 , G11C11/409 , H03K19/00 , H03K19/096 , G11C7/00
CPC分类号： G11C7/1051
摘要： A method of controlling the buffering of output data by synchronizing with an external system clock, including the steps of generating an internal clock pulse, transferring data from a chip to a pair of data output lines in response to the internal clock pulse, generating an output mode control signal in synchronism with the internal clock pulse, gating the output mode control signal from the first edge of the internal clock pulse to the first edge of the next internal clock pulse to produce an output control signal, and driving data output to an output pad in response to the output control signal is disclosed. A data output buffer control apparatus of a synchronous semiconductor memory device operating in synchronism with an externally applied system clock pulse is also disclosed, which apparatus has an internal clock pulse generator for generating an internal clock pulse in response to the system clock pulse, an output register for transmitting data from the inside of the chip to a pair of data output lines in synchronism with the first edge of the system clock pulse, an output mode control signal generator for generating a predetermined output mode control signal in synchronism with the system clock pulse, an output buffer control means for gating the output mode control signal from the first edge to the second edge of an internal clock pulse to create an output control signal, and a data output means for driving the output of the output register in response to the output control signal of the output buffer control means.
摘要翻译：一种通过与外部系统时钟同步来控制输出数据的缓冲的方法，包括产生内部时钟脉冲的步骤，响应于内部时钟脉冲将数据从芯片传送到一对数据输出线，产生一个输出模式控制信号与内部时钟脉冲同步，将输出模式控制信号从内部时钟脉冲的第一个边缘选通到下一个内部时钟脉冲的第一个边沿，以产生输出控制信号，并将数据输出驱动到输出公开了响应于输出控制信号的焊盘。还公开了与外部施加的系统时钟脉冲同步工作的同步半导体存储器件的数据输出缓冲器控制装置，该装置具有用于响应系统时钟脉冲产生内部时钟脉冲的内部时钟脉冲发生器，输出寄存器，用于与系统时钟脉冲的第一边沿同步地从芯片的内部传输数据到一对数据输出线;输出模式控制信号发生器，用于与系统时钟脉冲同步地产生预定的输出模式控制信号输出缓冲器控制装置，用于将输出模式控制信号从内部时钟脉冲的第一边缘到第二边缘选通以产生输出控制信号;以及数据输出装置，用于响应于所述输出控制信号驱动输出寄存器的输出输出缓冲器控制装置的输出控制信号。

7. 发明授权

US09053936B2 Layout method of semiconductor device with junction diode for preventing damage due to plasma charge 有权
标题翻译：具有结二极管的半导体器件的布局方法，用于防止等离子体电荷引起的损坏
公开(公告)号：US09053936B2
公开(公告)日：2015-06-09
申请号：US13613976
申请日：2012-09-13
申请人： Soo-Young Kim , Jong-Hak Won
发明人： Soo-Young Kim , Jong-Hak Won
IPC分类号： H01L27/02 , H01L27/06
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A method for forming a unit layout pattern includes: forming first through third active regions in the unit layout pattern, each of the first through third active regions aligning and extending along a length in a first direction and having a width in a second direction perpendicular to the first direction; forming first and second gate regions on the first and second active regions, the first and second gate regions electrically connected to each other; forming the first active region of a first conductive type within a second conductive type well region; forming the second active region of a second conductive type; and forming the third active region connected with the first and second gate regions to form a junction diode, the third active region being located between the first or the second active region and an end of the length in the first direction of the unit pattern.
摘要翻译：一种用于形成单元布局图案的方法包括：以单元布局图案形成第一至第三有源区域，第一至第三有源区域中的每一个沿着第一方向的长度对准并延伸，并且具有垂直于第一方向的第二方向的宽度第一个方向在所述第一和第二有源区上形成第一和第二栅极区，所述第一和第二栅极区彼此电连接; 在第二导电类型阱区内形成第一导电类型的第一有源区; 形成第二导电类型的第二有源区; 以及形成与所述第一和第二栅极区域连接以形成结二极管的所述第三有源区，所述第三有源区位于所述第一或第二有源区之间，并且位于所述单位图案的所述第一方向上的长度的端部。

8. 发明申请

US20130011982A1 LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE 审中-公开
标题翻译：具有连接二极管的半导体器件的布局方法，用于防止等离子体充电造成的损坏
公开(公告)号：US20130011982A1
公开(公告)日：2013-01-10
申请号：US13613976
申请日：2012-09-13
申请人： Soo-Young Kim , Jong-Hak Won
发明人： Soo-Young Kim , Jong-Hak Won
IPC分类号： H01L21/8234
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.
摘要翻译：用于防止由等离子体电荷引起的损坏的结二极管的布局方法包括：以单元布局图形形成有源层以形成多个有源区; 形成栅极层以在所述有源区上形成多个栅极区; 在阱层内的多个有源区域中的至少一个中形成第一导电型掺杂区，其中形成第二导电类型阱区以形成第一导电型有源区; 在所述第二导电类型阱区域外的所述多个有源区域中的至少一个中形成第二导电型掺杂区域，以形成第二导电型有源区域; 以及形成与所述栅极区域连接的第二导电型掺杂区域，以在所述第一和第二导电型有源区域之间的至少一个有源区域中形成结二极管。

9. 发明授权

US08288223B2 Layout method of semiconductor device with junction diode for preventing damage due to plasma charge 有权
标题翻译：具有结二极管的半导体器件的布局方法，用于防止等离子体电荷引起的损坏
公开(公告)号：US08288223B2
公开(公告)日：2012-10-16
申请号：US13364362
申请日：2012-02-02
申请人： Soo-Young Kim , Jong-Hak Won
发明人： Soo-Young Kim , Jong-Hak Won
IPC分类号： H01L21/8234
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.
摘要翻译：用于防止由等离子体电荷引起的损坏的结二极管的布局方法包括：以单元布局图形形成有源层以形成多个有源区; 形成栅极层以在所述有源区上形成多个栅极区; 在阱层内的多个有源区域中的至少一个中形成第一导电型掺杂区，其中形成第二导电类型阱区以形成第一导电型有源区; 在所述第二导电类型阱区域外的所述多个有源区域中的至少一个中形成第二导电型掺杂区域，以形成第二导电型有源区域; 以及形成与所述栅极区域连接的第二导电型掺杂区域，以在所述第一和第二导电型有源区域之间的至少一个有源区域中形成结二极管。

10. 发明申请

US20120149160A1 LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE 有权
标题翻译：具有连接二极管的半导体器件的布局方法，用于防止等离子体充电造成的损坏
公开(公告)号：US20120149160A1
公开(公告)日：2012-06-14
申请号：US13364362
申请日：2012-02-02
申请人： Soo-Young Kim , Jong-Hak Won
发明人： Soo-Young Kim , Jong-Hak Won
IPC分类号： H01L21/336
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.
摘要翻译：用于防止由等离子体电荷引起的损坏的结二极管的布局方法包括：以单元布局图形形成有源层以形成多个有源区; 形成栅极层以在所述有源区上形成多个栅极区; 在阱层内的多个有源区域中的至少一个中形成第一导电型掺杂区，其中形成第二导电类型阱区以形成第一导电型有源区; 在所述第二导电类型阱区域外部的所述多个有源区域中的至少一个中形成第二导电型掺杂区域，以形成第二导电型有源区域; 以及形成与所述栅极区域连接的第二导电型掺杂区域，以在所述第一和第二导电型有源区域之间的至少一个有源区域中形成结二极管。

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