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    • 3. 发明申请
    • MIMO ANTENNA RECEIVING APPARATUS AND RECEIVING METHOD
    • MIMO天线接收装置和接收方法
    • US20090154587A1
    • 2009-06-18
    • US12238082
    • 2008-09-25
    • Minho CHEONGYu-Ro LEEJong -Ee OHSok-Kyu LEE
    • Minho CHEONGYu-Ro LEEJong -Ee OHSok-Kyu LEE
    • H04L1/02H04B7/02H04B1/10
    • H04B7/0417H04L1/0631
    • Provided is a reception apparatus and method of a Multiple Input Multiple Output (MIMO) system that receives a plurality of different data streams in a multiple cell environment. The reception apparatus for receiving a plurality of different data streams in a multiple input multiple output (MIMO) antenna system includes a data stream detector for detecting each data stream by removing interference between the different data streams while maintaining channel information; and a cochannel interference (CCI) remover for removing cochannel interference from each data stream detected in the data stream detector. The present invention can remove cochannel interference and increase channel capacity to thereby acquire both diversity gain and multiplexing gain.
    • 提供了一种在多小区环境中接收多个不同数据流的多输入多输出(MIMO)系统的接收装置和方法。 用于在多输入多输出(MIMO)天线系统中接收多个不同数据流的接收装置包括:数据流检测器,用于通过在保持信道信息的同时消除不同数据流之间的干扰来检测每个数据流; 以及用于从数据流检测器中检测到的每个数据流去除同信道干扰的同信道干扰(CCI)去除器。 本发明可以消除同信道干扰并增加信道容量,从而获得分集增益和复用增益。
    • 4. 发明申请
    • APPARATUS AND METHOD FOR CODING QC-LDPC CODE
    • 用于编码QC-LDPC码的设备和方法
    • US20100162074A1
    • 2010-06-24
    • US12642463
    • 2009-12-18
    • Jong-Ee OHMinho CHEONGYu-Ro LEESok-Kyu LEEYongho LEE
    • Jong-Ee OHMinho CHEONGYu-Ro LEESok-Kyu LEEYongho LEE
    • H03M13/05G06F11/10
    • H03M13/116H03M13/6527H03M13/6544H04L1/0041H04L1/0057
    • A high-speed quasi-cyclic low density parity check (QC-LDPC) coding apparatus for coding inputted information into a generator matrix having a dual diagonal matrix format includes: a parity bit generation unit configured to generate an arbitrary parity bit; a temporary parity bit generation unit configured to constitute the inputted information with circulants, and shift and combine the respective circulants at each row to generate a temporary parity bit; a corrected bit generation unit configured to generate corrected bits of parity bits by using an output of the temporary parity bit generation unit; and a parity bit correction unit configured to correct the temporary parity bit by reflecting an output of the corrected bit generation unit to the output of the temporary parity bit generation unit.
    • 用于将输入的信息编码成具有双对角矩阵格式的生成矩阵的高速准循环低密度奇偶校验(QC-LDPC)编码装置包括:奇偶校验位生成单元,被配置为生成任意奇偶校验位; 临时奇偶校验位生成单元,被配置为构成具有循环的输入信息,并且移位并组合各行的各个循环以产生临时奇偶校验位; 校正位生成单元,其通过使用所述临时奇偶校验位生成单元的输出来生成校正位的校验位; 以及奇偶校验位校正单元,被配置为通过将校正的位生成单元的输出反映到临时奇偶校验位产生单元的输出来校正临时奇偶校验位。
    • 6. 发明申请
    • APPARATUS AND METHOD FOR DECODING LDPC CODE BASED ON PROTOTYPE PARITY CHECK MATRIXES
    • 基于原型奇偶校验矩阵来解码LDPC码的装置和方法
    • US20090158121A1
    • 2009-06-18
    • US12166866
    • 2008-07-02
    • Jong-Ee OHChanho YOONCheol-Hui RYUEun-Young CHOISok-Kyu LEE
    • Jong-Ee OHChanho YOONCheol-Hui RYUEun-Young CHOISok-Kyu LEE
    • H03M13/05G06F11/07
    • H03M13/116H03M13/1137H03M13/1185H03M13/1188H03M13/6516
    • Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.
    • 提供了一种基于原型奇偶校验矩阵对低密度奇偶校验(LDPC)码进行解码的装置和方法。 该装置包括:奇偶校验矩阵选择装置,用于根据子矩阵大小确定多个原型奇偶校验矩阵;以及用于处理奇偶校验矩阵的并行化图; 用于根据子矩阵大小和并行化图形接收输入比特的对数似然概率值的位输入装置; 校验矩阵处理装置,用于基于所接收的对数似然概率值和所确定的多原型奇偶校验矩阵,顺序对奇偶校验矩阵执行部分并行处理; 以及位处理装置,用于基于部分并行处理的奇偶校验矩阵值确定位电平,并根据子矩阵大小和并行化图形恢复输入位。