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    • 4. 发明授权
    • Thin film transistor array substrate and method of fabricating the same
    • 薄膜晶体管阵列基板及其制造方法
    • US07525120B2
    • 2009-04-28
    • US11716690
    • 2007-03-12
    • Kyoung Mook LeeSeung Hee NamJae Young Oh
    • Kyoung Mook LeeSeung Hee NamJae Young Oh
    • H01L29/04
    • H01L27/124G02F1/1362G02F2001/136236H01L27/1288H01L29/66765
    • A thin film transistor array substrate includes a gate line formed on a substrate, a data line formed on the substrate intersecting with the gate line to define a pixel region, a thin film transistor formed at the intersection of the gate line and the data line, the thin film transistor including gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode and the substrate, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer on the semiconductor layer, and a source electrode and a drain electrode on the ohmic contact layer, and a transparent electrode material within the pixel region and connected to the drain electrode of the thin film transistor, wherein the gate insulating layer includes a gate insulating pattern underlying the data line and the transparent electrode material, and covering the gate line.
    • 薄膜晶体管阵列基板包括形成在基板上的栅极线,形成在与栅极线交叉以限定像素区域的基板上的数据线,形成在栅极线和数据线的交叉处的薄膜晶体管, 所述薄膜晶体管包括形成在所述基板上的栅极电极,形成在所述栅极电极和所述基板上的栅极绝缘层,形成在所述栅极绝缘层上的半导体层,所述半导体层上的欧姆接触层以及源电极和 漏极电极和像素区域内的透明电极材料,并连接到薄膜晶体管的漏电极,其中栅极绝缘层包括位于数据线下方的栅绝缘图案和透明电极材料,以及 覆盖门线。
    • 6. 发明授权
    • Method for fabricating array substrate of liquid crystal display device
    • 制造液晶显示装置阵列基板的方法
    • US07001796B2
    • 2006-02-21
    • US10875318
    • 2004-06-25
    • Heung Lyul ChoSeung Hee NamJae Young Oh
    • Heung Lyul ChoSeung Hee NamJae Young Oh
    • H01C21/00
    • H01L27/1288H01L27/1214H01L27/124
    • An array substrate of a liquid crystal display (LCD) device and a method for fabricating the same is disclosed, to decrease the unit cost and time of fabrication by decreasing the usage count of mask, which includes simultaneously forming a gate line, a gate electrode and a pixel electrode on a substrate; depositing a gate insulating layer and an active layer on an entire surface of the substrate including the gate line; patterning the gate insulating layer and the active layer to remain on the gate line and the gate electrode; selectively removing the active layer above the gate line; forming a data line perpendicular to the gate line and source/drain electrodes; and depositing a passivation layer on the entire surface of the substrate including the data line.
    • 公开了一种液晶显示器(LCD)器件的阵列基板及其制造方法,通过减少包括同时形成栅极线的掩模的使用次数来减小制造的单位成本和时间,栅电极 和基板上的像素电极; 在包括栅极线的基板的整个表面上沉积栅极绝缘层和有源层; 图案化栅极绝缘层和有源层以保留在栅极线和栅电极上; 选择性地去除栅极线上方的有源层; 形成垂直于栅极线和源极/漏极的数据线; 以及在包括所述数据线的所述衬底的整个表面上沉积钝化层。
    • 9. 发明授权
    • Array substrate for liquid crystal display and fabrication method thereof
    • 液晶显示器用阵列基板及其制造方法
    • US07471350B2
    • 2008-12-30
    • US10663774
    • 2003-09-17
    • Kyoung Mook LeeSeung Hee NamJae Young Oh
    • Kyoung Mook LeeSeung Hee NamJae Young Oh
    • G02F1/136G02F1/1343
    • G02F1/136286G02F1/136227G02F1/136277
    • Disclosed is an array substrate for a liquid crystal display, including: a substrate; a gate line and a thin film transistor having a gate electrode, a source electrode, a drain electrode and an active layer formed over the substrate; an interlayer insulating layer formed on the thin film transistor; a first gate redundancy line formed on the interlayer insulating layer, and connected electrically with one of the gate electrode and the gate line through a first gate contact hole and formed of the same material as the source and drain electrodes; a passivation layer provided on the first gate redundancy line and the interlayer insulating layer; and a pixel electrode electrically connected with the drain electrode through the drain contact hole formed in the passivation layer.
    • 公开了一种液晶显示器用阵列基板,包括:基板; 栅极线和薄膜晶体管,其具有形成在衬底上的栅电极,源电极,漏电极和有源层; 形成在薄膜晶体管上的层间绝缘层; 第一栅极冗余线,形成在所述层间绝缘层上,并且通过第一栅极接触孔与所述栅极电极和所述栅极线中的一个电连接并由与所述源极和漏极电极相同的材料形成; 设置在第一栅极冗余线和层间绝缘层上的钝化层; 以及通过形成在钝化层中的漏极接触孔与漏电极电连接的像素电极。