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1. 发明授权

US06226660B1 Efficient method of implementing random number generators 有权
标题翻译：实现随机数发生器的有效方法
公开(公告)号：US06226660B1
公开(公告)日：2001-05-01
申请号：US09148899
申请日：1998-09-08
申请人： Jong Bae Kim , Hyeong Cheol Oh , Goo Young Park
发明人： Jong Bae Kim , Hyeong Cheol Oh , Goo Young Park
IPC分类号： G06F102
CPC分类号： G06F7/582
摘要： The present invention provides a method of implementing random number generators, which makes efficient hardware implementations possible, in a way of converting the multiplication and addition operations and the modulo operations into a series of addition operations.
摘要翻译：本发明提供了一种实现随机数发生器的方法，其使得有效的硬件实现成为可能，其方法是将乘法运算和加法运算以及模运算转换为一系列加法运算。

2. 发明申请

US20100064276A1 JAVA BYTECODE TRANSLATING METHOD 失效
标题翻译： JAVA BYTECODE TRANSLATING方法
公开(公告)号：US20100064276A1
公开(公告)日：2010-03-11
申请号：US12514430
申请日：2008-08-19
申请人： Jong Sung Lee , Hyeong Cheol Oh , Hyun Gyu Kim , Kwan Young Kim
发明人： Jong Sung Lee , Hyeong Cheol Oh , Hyun Gyu Kim , Kwan Young Kim
IPC分类号： G06F9/44
CPC分类号： G06F9/30174 , G06F9/44521 , G06F9/45508
摘要： Provided is a Java bytecode translating method which includes: a bytecode fetch step (S1 10) that fetches a Java bytecode from a Java class file; a static field address detection and data processing step (S140) which gains access to a field (130) according to a first field address (FA1) and processes data; a static field address storage step (S 150) that stores a first upper field address (FAU1) including upper bits among bits of the first field address (FA1) in a first storage portion (110), and which stores a first lower field address (FAD1) including remainder lower bits excluding the first upper field address (FAU1) among the bits of the first field address (FA1) in an operand field (120b); a static operation code translating step (S 160) that translates an operation code stored in an operation code field (120a) into a new static field accessing operation code (NOPA); a first field address creation step (S240) that creates a second field address (FA2); and a first data processing step (S250) that gains access to the field (130) according to a second field address (F A2) and processes data.
摘要翻译：提供了一种Java字节码翻译方法，其包括：从Java类文件获取Java字节码的字节码获取步骤（S110）; 静态场地址检测和数据处理步骤（S140），其根据第一字段地址（FA1）访问字段（130）并处理数据; 静态场地址存储步骤（S150），其在第一存储部分（110）中存储包括第一字段地址（FA1）的比特之中的高位的第一上场地址（FAU1），并且存储第一下场地址（FAD1），包括除了操作数字段（120b）中的第一字段地址（FA1）的位之外的除了第一上场地址（FAU1）之外的其余较低位; 将存储在操作码字段（120a）中的操作代码转换为新的静态字段访问操作码（NOPA）的静态操作码转换步骤（S160）; 创建第二字段地址（FA2）的第一字段地址创建步骤（S240）; 以及根据第二字段地址（F A2）获得对字段（130）的访问并处理数据的第一数据处理步骤（S250）。

3. 发明授权

US08291391B2 Java bytecode translating method 失效
标题翻译： Java字节码转换方法
公开(公告)号：US08291391B2
公开(公告)日：2012-10-16
申请号：US12514430
申请日：2008-08-19
申请人： Jong Sung Lee , Hyeong Cheol Oh , Hyun Gyu Kim , Kwan Young Kim
发明人： Jong Sung Lee , Hyeong Cheol Oh , Hyun Gyu Kim , Kwan Young Kim
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/30174 , G06F9/44521 , G06F9/45508
摘要： Provided is a Java bytecode translating method which includes: a bytecode fetch step (S1 10) that fetches a Java bytecode from a Java class file; a static field address detection and data processing step (S140) which gains access to a field (130) according to a first field address (FA1) and processes data; a static field address storage step (S 150) that stores a first upper field address (FAU1) including upper bits among bits of the first field address (FA1) in a first storage portion (110), and which stores a first lower field address (FAD1) including remainder lower bits excluding the first upper field address (FAU1) among the bits of the first field address (FA1) in an operand field (120b); a static operation code translating step (S 160) that translates an operation code stored in an operation code field (120a) into a new static field accessing operation code (NOPA); a first field address creation step (S240) that creates a second field address (FA2); and a first data processing step (S250) that gains access to the field (130) according to a second field address (F A2) and processes data.
摘要翻译：提供了一种Java字节码翻译方法，其包括：从Java类文件获取Java字节码的字节码获取步骤（S110）; 静态场地址检测和数据处理步骤（S140），其根据第一字段地址（FA1）访问字段（130）并处理数据; 静态场地址存储步骤（S150），其在第一存储部分（110）中存储包括第一字段地址（FA1）的比特之中的高位的第一上场地址（FAU1），并且存储第一下场地址（FAD1），包括除了操作数字段（120b）中的第一字段地址（FA1）的位之外的除了第一上场地址（FAU1）之外的其余较低位; 将存储在操作码字段（120a）中的操作代码转换为新的静态字段访问操作码（NOPA）的静态操作码转换步骤（S160）; 创建第二字段地址（FA2）的第一字段地址创建步骤（S240）; 以及根据第二字段地址（F A2）获得对字段（130）的访问并处理数据的第一数据处理步骤（S250）。

4. 发明授权

US06631459B1 Extended instruction word folding apparatus 有权
标题翻译：扩展指令字折叠装置
公开(公告)号：US06631459B1
公开(公告)日：2003-10-07
申请号：US09644642
申请日：2000-08-24
申请人： Kyung Youn Cho , Jong Yoon Lim , Geun Taek Lee , Hyeong Cheol Oh , Hyun Gyu Kim , Byung Gueon Min , Heui Lee
发明人： Kyung Youn Cho , Jong Yoon Lim , Geun Taek Lee , Hyeong Cheol Oh , Hyun Gyu Kim , Byung Gueon Min , Heui Lee
IPC分类号： G06F928
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3016 , G06F9/30185
摘要： An apparatus includes an instruction word storage for storing a plurality of general instruction words and extended instruction words, a temporary storage unit including a plurality of buffers for pre-fetching and storing the plurality of instruction words from the instruction word storage, an instruction word search unit for receiving and decoding the plurality of instruction words pre-fetched and outputting a position signal of a general instruction word and the positions of one or more successive extended instruction words stored in the temporary storage a selector for selecting a buffer in which a general instruction word is stored and outputting the general instruction word sequentially, according to the position signal a general instruction word parser for receiving a general instruction word from the selector and outputting a plurality of control signals for executing the general instruction word simultaneously, an extended data parser is provided for performing an operational processing of operands of one or more successive extended instruction words stored in each buffer of the temporary storage according to the position signal.
摘要翻译：一种装置，包括用于存储多个通用指令字和扩展指令字的指令字存储器，包括用于从指令字存储器预取和存储多个指令字的多个缓冲器的临时存储单元，指令字搜索单元，用于接收和解码预取的多个指令字，并输出一般指令字的位置信号和存储在临时存储器中的一个或多个连续扩展指令字的位置，选择器用于选择缓冲器，其中一般指令存储字，并根据位置信号顺序地输出一般指令字，一般指令字解析器用于从选择器接收一般指令字并输出用于同时执行通用指令字的多个控制信号，扩展数据解析器是提供用于执行操作p 根据位置信号对存储在临时存储器的每个缓冲器中的一个或多个连续扩展指令字的操作数进行处理。

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