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1. 发明授权

US4354229A Loop initialization mechanism for a peer-to-peer communication system 失效
标题翻译：对等通信系统的环路初始化机制
公开(公告)号：US4354229A
公开(公告)日：1982-10-12
申请号：US129052
申请日：1980-03-10
申请人： Jonathan B. Davis , Charles S. Lanier , Daniel T. W. Sze , Leonard Weiss
发明人： Jonathan B. Davis , Charles S. Lanier , Daniel T. W. Sze , Leonard Weiss
IPC分类号： H04L5/22 , G06F13/00 , H04L7/00 , H04L12/42 , H04L12/437 , G06F15/16
CPC分类号： H04L12/422 , H04L12/437
摘要： In a loop-structured communication system interconnecting a plurality of data processors without central controller, stations comprise modems which can start loop operation and achieve synchronous frame transmission around the loop through all participating stations.In an initialization procedure after system start or after loss of frame synchronization on the loop, modems select a temporary master station.The temporary master will adapt total loop delay to be an integer multiple of the basic frame period, and will transmit available frames. All active modems adapt their timing to the circulating stream of frames until the whole loop and all participating stations are synchronized.Synchronization conditions are continuously monitored in all stations to start resynchronization or initialization procedures if necessary. In a specific arrangement, the location of a loop failure which prevents establishment of synchronization can be determined.All initialization and synchronization operations are handled by the modems without participation by other functional units or by the host processing system of any station.
摘要翻译：在不具有中央控制器的多个数据处理器互连的环路结构化通信系统中，站包括调制解调器，其可以开始循环操作，并通过所有参与站实现循环周期的同步帧传输。在系统启动或循环丢帧后的初始化过程中，调制解调器选择一个临时主站。临时主设备将总循环延迟调整为基本帧周期的整数倍，并传送可用帧。所有活动的调制解调器将其时序调整到循环的帧流，直到整个循环和所有参与站同步。在所有站点中连续监视同步条件，以便在必要时启动重新同步或初始化程序。在具体的布置中，可以确定防止建立同步的环路故障的位置。所有初始化和同步操作都由调制解调器处理，而不受其他功能单元或任何站的主机处理系统的参与。

2. 发明授权

US4482999A Method of transmitting information between stations attached to a _unidirectional transmission ring 失效
标题翻译：在单向传输环附近的站之间传输信息的方法
公开(公告)号：US4482999A
公开(公告)日：1984-11-13
申请号：US326291
申请日：1981-12-01
申请人： Philippe A. Janson , Hans R. Mueller , Daniel T. W. Sze
发明人： Philippe A. Janson , Hans R. Mueller , Daniel T. W. Sze
IPC分类号： H04L12/433 , H04L12/64 , H04J6/00
CPC分类号： H04L12/64 , H04L12/433
摘要： In a ring communication system comprising several stations, access to the ring is granted to one station at a time by a circulating token indication. A method is provided guaranteeing a transmission opportunity for synchronous or circuit-switched data in periodic time intervals to authorized stations. A CS monitor station issues a frame header which is marked in a specific bit position to allow only authorized stations to transmit their synchronous data together with a destination address. In a first embodiment, a single frame comprises a plurality of slots each having a free/busy indication, a destination address field and a field for synchronous data, and each authorized station can occupy one such slot. In a second embodiment, a marked frame can be used by only one authorized station for transmitting synchronous data, but a new marked frame header is reissued until all authorized stations around the ring have transmitted synchronous data.

3. 发明授权

US4363093A Processor intercommunication system 失效
标题翻译：处理器互通系统
公开(公告)号：US4363093A
公开(公告)日：1982-12-07
申请号：US129053
申请日：1980-03-10
申请人： Michael I. Davis , Daniel T. W. Sze
发明人： Michael I. Davis , Daniel T. W. Sze
IPC分类号： H04L5/22 , G06F13/00 , G06F15/173 , G06F15/16
CPC分类号： G06F15/17337
摘要： A processor intercommunication system includes a plurality of stations which are interconnected by a transmission link, each station having an associated processor. Further, each station comprises means which provide a data link protocol mechanism for establishing and maintaining a multiplicity of logical connections or transfer sessions between the station and several other stations. Thus application programs of all kinds in the processors can communicate with programs or data files in remote processors and need not be involved in communication operations which are handled by the stations. Link access circuitry is provided also in each station for absorbing the physical and topological characteristics of the transmission link so that the data protocol circuitry establishing and maintaining logical connections is independent of these characteristics.
摘要翻译：处理器互通系统包括通过传输链路互连的多个站，每个站具有相关联的处理器。此外，每个站包括提供数据链路协议机制的装置，用于建立和维护多个逻辑连接或在站与其他几个站之间的传送会话。因此，处理器中的各种应用程序可以与远程处理器中的程序或数据文件进行通信，并且不需要参与由站处理的通信操作。在每个站中还提供链路接入电路，用于吸收传输链路的物理和拓扑特性，使得建立和维持逻辑连接的数据协议电路与这些特性无关。

4. 发明授权

US4346474A Even-odd parity checking for synchronous data transmission 失效
标题翻译：用于同步数据传输的偶奇偶校验
公开(公告)号：US4346474A
公开(公告)日：1982-08-24
申请号：US165581
申请日：1980-07-03
申请人： Daniel T. W. Sze
发明人： Daniel T. W. Sze
IPC分类号： G06F11/10 , H03M13/00 , H04L1/00
CPC分类号： H04L1/0057
摘要： A synchronous data transmission system between remote stations is shown wherein data is transmitted parallel by bit serial by group over a plurality of parallel lines extending between sending and receiving stations. A parity line is also included in the transmission system for checking errors and a clock line is included for synchronization of the parallel data being transmitted. Information is transmitted from one station to another with alternating even and odd parity for succeeding groups of parallel data. The information is checked at the receiving station for even-even or odd-odd parity in succeeding groups of data. Longitudinal redundancy checking (LRC) is also added to the checking at a receiving station. The combination of the even and odd parity checking and the LRC checking provides a level of data transmission error checking which is almost as effective in finding errors as a far more costly CRC checking mechanism. The checking arrangement is adaptable to serial-by-bit transmission systems, as well.
摘要翻译：示出了远程站之间的同步数据传输系统，其中通过在发送站和接收站之间延伸的多个并行线路上逐位地逐行地传送数据。在用于检查错误的传输系统中还包括奇偶校验线，并且包括时钟线以用于正在发送的并行数据的同步。信息从一个站发送到另一个站，对于后续的并行数据组，具有交替的奇偶校验。在接收站检查信息，以获得后续数据组中的偶数或奇数奇偶校验。纵向冗余检查（LRC）也被添加到接收站的检查。偶校验和奇校验和LRC检查的组合提供了数据传输错误检查的水平，其几乎与查找错误一样有效，因为成本更高的CRC校验机制。检查装置也适用于逐位传输系统。

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