专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07917328B2 Tracking thermal mini-cycle stress 失效
标题翻译：跟踪热微循环应力
公开(公告)号：US07917328B2
公开(公告)日：2011-03-29
申请号：US12194606
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
IPC分类号： G06F19/00
CPC分类号： G06F11/3058
摘要： Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.
摘要翻译：提供了组装过程中组装体验的温度偏移。确定组件是否已经超出预定寿命目标的使用。响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。将累积的绩效值与累积压力的绩效预算进行比较。响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

2. 发明申请

US20100049466A1 Tracking Thermal Mini-Cycle Stress 失效
标题翻译：跟踪热微循环应力
公开(公告)号：US20100049466A1
公开(公告)日：2010-02-25
申请号：US12194606
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
IPC分类号： G06F17/00 , G08B1/08
CPC分类号： G06F11/3058
摘要： Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.
摘要翻译：提供了组装过程中组装体验的温度偏移。确定组件是否已经超出预定寿命目标的使用。响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。将累积的绩效值与累积压力的绩效预算进行比较。响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

3. 发明授权

US08214658B2 Enhanced thermal management for improved module reliability 失效
标题翻译：增强热管理，提高模块可靠性
公开(公告)号：US08214658B2
公开(公告)日：2012-07-03
申请号：US12194620
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcolm S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcolm S. Ware , Roger D. Weekly
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.
摘要翻译：提供了数据处理系统中组件分层的缓解效应。从数据处理系统中的一个或多个传感器接收信号。确定信号是否指示已经达到或超过多个阈值中的一个阈值。响应于指示已经达到或超过多个阈值中的一个阈值的信号，确定一个阈值是低温阈值还是高温阈值。响应于一个阈值是低温阈值，开始多个动作之一以增加数据处理系统的温度，从而减轻数据处理系统中组件的分层影响。

4. 发明申请

US20100049995A1 Enhanced Thermal Management for Improved Module Reliability 失效
标题翻译：增强热管理，提高模块可靠性
公开(公告)号：US20100049995A1
公开(公告)日：2010-02-25
申请号：US12194620
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcolm S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcolm S. Ware , Roger D. Weekly
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.
摘要翻译：提供了数据处理系统中组件分层的缓解效应。从数据处理系统中的一个或多个传感器接收信号。确定信号是否指示已经达到或超过多个阈值中的一个阈值。响应于指示已经达到或超过多个阈值中的一个阈值的信号，确定一个阈值是低温阈值还是高温阈值。响应于一个阈值是低温阈值，开始多个动作之一以增加数据处理系统的温度，从而减轻数据处理系统中组件的分层影响。

5. 发明授权

US08742565B2 Ball grid array with improved single-ended and differential signal performance 有权
标题翻译：具有改进的单端和差分信号性能的球栅阵列
公开(公告)号：US08742565B2
公开(公告)日：2014-06-03
申请号：US13687218
申请日：2012-11-28
申请人： Roger D. Weekly , Yaping Zhou
发明人： Roger D. Weekly , Yaping Zhou
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/50 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/48225 , H01L2224/48227 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.
摘要翻译：一种用于分配电源和接地引脚以及用于球栅阵列半导体封装的单端或差分信号对的改进的系统和方法。在某些实施例中，系统使用六边形图案，其中网格可以由多个嵌套的六边形图案表示。

6. 发明授权

US08325490B2 Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
标题翻译：具有带段的参考平面空隙的电路制造和设计技术
公开(公告)号：US08325490B2
公开(公告)日：2012-12-04
申请号：US12823316
申请日：2010-06-25
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H05K1/11
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
摘要翻译：具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起信号承载PTH的顶部（或底部）到传输线参考平面。为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持信号路径导体。

7. 发明授权

US08295058B2 Structure for enhancing reference return current conduction 失效
标题翻译：用于增强参考回流导通的结构
公开(公告)号：US08295058B2
公开(公告)日：2012-10-23
申请号：US12641381
申请日：2009-12-18
申请人： Joseph J. Cahill , Anand Haridass , Roger D. Weekly
发明人： Joseph J. Cahill , Anand Haridass , Roger D. Weekly
IPC分类号： H05K1/11 , H05K7/14 , H05K9/00
CPC分类号： H05K1/0251 , G06F17/5077 , H05K1/162 , H05K2201/09509 , H05K2201/09536
摘要： An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.
摘要翻译：提供了一种装置，其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。所述至少一个内部参考平面设置在至少两个信令平面之间。该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。盲/埋通孔穿过至少一个内部参考平面。该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。至少一个第一导电特征与信号盲/掩埋通孔紧密接近，并且增加了装置参考平面中电流的电容耦合。

8. 发明授权

US07844925B2 System and method for power domain optimization 有权
标题翻译：电力域优化的系统和方法
公开(公告)号：US07844925B2
公开(公告)日：2010-11-30
申请号：US11753644
申请日：2007-05-25
申请人： Tingdong Zhou , Michael A. Christo , Julio A. Maldonado , Roger D. Weekly
发明人： Tingdong Zhou , Michael A. Christo , Julio A. Maldonado , Roger D. Weekly
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： H05K1/0262 , G06F17/5068 , G06F2217/78 , H05K3/0005 , H05K2201/093 , H05K2201/09336 , H05K2201/09345 , H05K2201/09663
摘要： A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on the DC properties and the PNI properties of the power plane. The method further includes replacing the identified victim areas with ground (GND) shapes to form a modified power plane.
摘要翻译：一种用于电子电路电源平面设计的方法包括分析电子电路的电源平面的直流（DC）特性。该方法包括基于电力平面的DC特性和PNI特性来分析功率平面的功率网络电感（PNI）特性和识别具有预定电流密度特性的功率平面的受害区域。该方法还包括用地（GND）形状替换所识别的受害区域，以形成修改后的电力平面。

9. 发明申请

US20090048794A1 Method for Detecting Noise Events in Systems with Time Variable Operating Points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US20090048794A1
公开(公告)日：2009-02-19
申请号：US12262021
申请日：2008-10-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F19/00
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

10. 发明授权

US07460986B2 System DC Analysis Methodology 有权
标题翻译：系统直流分析方法
公开(公告)号：US07460986B2
公开(公告)日：2008-12-02
申请号：US11380058
申请日：2006-04-25
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5036
摘要： A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.
摘要翻译：提供了一种用于分层系统的功率传递分析和设计的方法。该方法包括建立与分级系统的每个元素相对应的模型，编译包含对应于分层系统的每个元素的模型的存储库，其中存储库包括网络列表，域列表，组件列表，引脚列表，和一个图层列表。该方法还包括对分层系统的每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化，以及从存储库中包含的模型组装系统模型。此外，该方法包括通过将系统模型转换为完全由电阻组成的扁平化系统模型，并在扁平化系统模型上运行模拟来平坦化系统模型。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式