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1. 发明授权

US08918351B2 Providing transposable access to a synapse array using column aggregation 有权
标题翻译：使用列聚合提供对突触阵列的可转位访问
公开(公告)号：US08918351B2
公开(公告)日：2014-12-23
申请号：US13562203
申请日：2012-07-30
申请人： John V. Arthur , John E. Barth, Jr. , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , John E. Barth, Jr. , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/02 , G06F15/18
CPC分类号： G06N3/02 , G06F15/18 , G06N3/063
摘要： Embodiments of the invention relate to providing transposable access to a synapse array using column aggregation. One embodiment comprises a neural network including a plurality of electronic axons, a plurality of electronic neurons, and a crossbar for interconnecting the axons with the neurons. The crossbar comprises a plurality of electronic synapses. Each synapse interconnects an axon with a neuron. The neural network further comprises a column aggregation module for transposable access to one or more synapses of the crossbar using column aggregation.
摘要翻译：本发明的实施方案涉及使用柱聚集来提供对突触阵列的可转位访问。一个实施例包括包括多个电子轴突，多个电子神经元和用于将轴突与神经元互连的交叉开关的神经网络。横杆包括多个电子突触。每个突触将轴突与神经元相互连接。所述神经网络还包括列聚集模块，用于使用柱聚集来转位地访问所述交叉开关的一个或多个突触。

2. 发明申请

US20140344201A1 PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING COLUMN AGGREGATION 有权
标题翻译：使用柱聚合提供可扩展的访问到一个SYNPSE阵列
公开(公告)号：US20140344201A1
公开(公告)日：2014-11-20
申请号：US13562203
申请日：2012-07-30
申请人： John V. Arthur , John E. Barth, JR. , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , John E. Barth, JR. , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/02 , G06F15/18 , G06N3/063
摘要： Embodiments of the invention relate to providing transposable access to a synapse array using column aggregation. One embodiment comprises a neural network including a plurality of electronic axons, a plurality of electronic neurons, and a crossbar for interconnecting the axons with the neurons. The crossbar comprises a plurality of electronic synapses. Each synapse interconnects an axon with a neuron. The neural network further comprises a column aggregation module for transposable access to one or more synapses of the crossbar using column aggregation.
摘要翻译：本发明的实施方案涉及使用柱聚集来提供对突触阵列的可转位访问。一个实施例包括包括多个电子轴突，多个电子神经元和用于将轴突与神经元互连的交叉开关的神经网络。横杆包括多个电子突触。每个突触将轴突与神经元相互连接。所述神经网络还包括列聚集模块，用于使用柱聚集来转位地访问所述交叉开关的一个或多个突触。

3. 发明授权

US09218564B2 Providing transposable access to a synapse array using a recursive array layout 有权
标题翻译：使用递归数组布局提供对突触阵列的转座访问
公开(公告)号：US09218564B2
公开(公告)日：2015-12-22
申请号：US13562195
申请日：2012-07-30
申请人： John V. Arthur , John E. Barth, Jr. , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , John E. Barth, Jr. , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/02 , G06N3/04 , G06N3/08
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
摘要翻译：本发明的实施例涉及使用递归阵列布局提供对突触阵列的可转位访问。一个实施例包括维持连接多个轴突和多个神经元的多个突触的突触权重，其中基于递归阵列布局维持突触权重。递归数组布局有助于对突触权重的可转位访问。通过访问递归阵列布局中相应连接突触的突触权重，通过相应的连接突触传达轴突和神经元之间的神经元尖峰事件。

4. 发明申请

US20150286923A1 PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE ARRAY LAYOUT 有权
标题翻译：使用一个重复的阵列布局提供可传输访问到一个快速阵列
公开(公告)号：US20150286923A1
公开(公告)日：2015-10-08
申请号：US13562195
申请日：2012-07-30
申请人： John V. Arthur , John E. Barth, JR. , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , John E. Barth, JR. , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
摘要翻译：本发明的实施例涉及使用递归阵列布局提供对突触阵列的可转位访问。一个实施例包括维持连接多个轴突和多个神经元的多个突触的突触权重，其中基于递归阵列布局维持突触权重。递归数组布局有助于对突触权重的可转位访问。通过访问递归阵列布局中相应连接突触的突触权重，通过相应的连接突触传达轴突和神经元之间的神经元尖峰事件。

5. 发明授权

US09189729B2 Scalable neural hardware for the noisy-OR model of Bayesian networks 有权
标题翻译：贝叶斯网络噪声或模型的可扩展神经硬件
公开(公告)号：US09189729B2
公开(公告)日：2015-11-17
申请号：US13562187
申请日：2012-07-30
申请人： John V. Arthur , Steven K. Esser , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , Steven K. Esser , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/04 , G06N3/08 , G06F7/58 , G06N7/00
CPC分类号： G06N3/08 , G06F7/582 , G06N3/04 , G06N3/0472 , G06N3/063 , G06N7/005
摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.
摘要翻译：本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。一个实施例包括神经核心电路，其包括用于产生随机数的伪随机数发生器。神经核心电路还包括多个输入电子轴突，多个神经模块以及将轴突与神经模块互连的多个电子突触。每个突触将轴突与神经模块相互连接。每个神经模块从相互联系的轴突接收进入的尖峰。每个神经模块表示噪声或门。每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。

6. 发明授权

US08909576B2 Neuromorphic event-driven neural computing architecture in a scalable neural network 有权
标题翻译：神经元事件驱动的神经计算架构在可扩展的神经网络中
公开(公告)号：US08909576B2
公开(公告)日：2014-12-09
申请号：US13235341
申请日：2011-09-16
申请人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/06 , G06N3/04 , G06N3/049 , G06N3/063
摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
摘要翻译：事件驱动神经网络包括多个互连的核心电路。每个核心电路包括具有互连多个数字电子神经元的多个数字突触的电子突触阵列。突触将突触前神经元的轴突与突触后神经元的枝晶相互连接。神经元集成输入尖峰，并响应于超过阈值的积分输入尖峰而产生尖峰事件。每个核心电路还具有接收尖峰事件的调度器，并且基于用于确定性事件递送的调度将突发事件传递到突触阵列中的选定轴突。

7. 发明申请

US20140114893A1 LOW-POWER EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN NEURAL NETWORKS 有权
标题翻译：神经网络中的低功率事件驱动神经计算体系结构
公开(公告)号：US20140114893A1
公开(公告)日：2014-04-24
申请号：US13149754
申请日：2011-05-31
申请人： John V. Arthur , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/08
CPC分类号： G06N3/08 , G06N3/049 , G06N3/063 , G11C11/54
摘要： A neural network includes an electronic synapse array of multiple digital synapses interconnecting a plurality of digital electronic neurons. Each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. Each neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. A decoder receives spike events sequentially and transmits the spike events to selected axons in the synapse array. An encoder transmits spike events corresponding to spiking neurons. A controller coordinates events from the synapse array to the neurons, and signals when neurons may compute their spike events within each time step, ensuring one-to-one correspondence with an equivalent software model. The synapse array includes an interconnecting crossbar that sequentially receives spike events from axons, wherein one axon at a time drives the crossbar, and the crossbar transmits synaptic events in parallel to multiple neurons.
摘要翻译：神经网络包括互连多个数字电子神经元的多个数字突触的电子突触阵列。每个突触将突触前神经元的轴突与突触后神经元的枝晶相互连接。每个神经元集成了输入尖峰，并响应于超过阈值的积分输入尖峰而产生尖峰事件。解码器顺序地接收尖峰事件并将突发事件发送到突触阵列中的选定轴突。编码器发送对应于尖峰神经元的尖峰事件。控制器协调从突触阵列到神经元的事件，并且当神经元可以在每个时间步长内计算它们的尖峰事件时，发出信号，确保与等效的软件模型一一对应。突触阵列包括从轴突顺序地接收尖峰事件的互连交叉开关，其中一次轴突一次驱动交叉开关，并且交叉开关将突触事件平行地传送到多个神经元。

8. 发明授权

US09269044B2 Neuromorphic event-driven neural computing architecture in a scalable neural network 有权
标题翻译：神经元事件驱动的神经计算架构在可扩展的神经网络中
公开(公告)号：US09269044B2
公开(公告)日：2016-02-23
申请号：US13585010
申请日：2012-08-14
申请人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/06 , G06N3/04 , G06N3/049 , G06N3/063
摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
摘要翻译：事件驱动神经网络包括多个互连的核心电路。每个核心电路包括具有互连多个数字电子神经元的多个数字突触的电子突触阵列。突触将突触前神经元的轴突与突触后神经元的枝晶相互连接。神经元集成输入尖峰，并响应于超过阈值的积分输入尖峰而产生尖峰事件。每个核心电路还具有接收尖峰事件的调度器，并且基于用于确定性事件递送的调度将突发事件传递到突触阵列中的选定轴突。

9. 发明申请

US20150302295A1 GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC NETWORK 有权
标题翻译：全球异地和同步同步（GALS）神经网络
公开(公告)号：US20150302295A1
公开(公告)日：2015-10-22
申请号：US13563333
申请日：2012-07-31
申请人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/08 , G06N3/04
CPC分类号： G06N3/04 , G06N3/049 , G06N3/063
摘要： Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.
摘要翻译：本发明的实施例涉及全球异步和局部同步神经网络。一个实施例包括生成分配给多个神经核心电路的同步信号。响应于同步信号，在至少一个核心电路中，处理由所述至少一个核心电路维持的传入尖峰事件以产生输出尖峰事件。尖峰事件通过包括多个异步路由器的路由结构在核心电路之间异步传送。

10. 发明授权

US09159020B2 Multiplexing physical neurons to optimize power and area 有权
标题翻译：复用物理神经元以优化功率和面积
公开(公告)号：US09159020B2
公开(公告)日：2015-10-13
申请号：US13619433
申请日：2012-09-14
申请人： Rodrigo Alcarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
发明人： Rodrigo Alcarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/063 , G06N3/02 , G06N3/04
CPC分类号： G06N3/049 , G06N3/02 , G06N3/063
摘要： Embodiments of the invention relate to a multiplexed neural core circuit. One embodiment comprises a neural core circuit including a memory device that maintains neuronal attributes for multiple neurons. The memory device has multiple entries. Each entry maintains neuronal attributes for a corresponding neuron. The core circuit further comprises a controller for managing the memory device and processing neuronal firing events targeting each neuron. The controller multiplexes computation and control logic for the neurons. In response to neuronal firing events targeting one of the neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates the firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.
摘要翻译：本发明的实施例涉及多路神经核心电路。一个实施例包括神经核心电路，其包括维持多个神经元的神经元属性的存储器件。存储设备有多个条目。每个条目保持相应神经元的神经元属性。核心电路还包括用于管理存储器件并处理针对每个神经元的神经元触发事件的控制器。控制器复用神经元的计算和控制逻辑。响应于针对其中一个神经元的神经元发射事件，控制器从存储器件的相应入口检索目标神经元的神经元属性，并且基于所检索的神经元属性来集成触发事件以产生目标神经元的触发事件。

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