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1. 发明授权

US6026488A Method for conditional hedge fetching into cache storage 失效
标题翻译：用于条件对冲取入缓存存储的方法
公开(公告)号：US6026488A
公开(公告)日：2000-02-15
申请号：US27153
申请日：1998-02-20
申请人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
发明人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/38
CPC分类号： G06F9/3804
摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to be fetched.
摘要翻译：一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复获取请求，否则数据不在高速缓存中，以在一个稍后时间，当确定正在执行的进程想要数据时，或者在确定正在执行的进程不需要要获取的数据的情况下从不重复该请求。

2. 发明授权

US6035392A Computer with optimizing hardware for conditional hedge fetching into cache storage 失效
标题翻译：具有优化硬件的计算机，用于将条件对冲提取到高速缓存存储中
公开(公告)号：US6035392A
公开(公告)日：2000-03-07
申请号：US26923
申请日：1998-02-20
申请人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
发明人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3804
摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.
摘要翻译：一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复该提取请求，该数据不在高速缓存中以在稍后重复该提取请求更确定正在执行的进程想要数据的时间，或者在确定正在执行的进程不需要他获取的数据的情况下，永远不会重复该请求。

3. 发明授权

US06079013A Multiprocessor serialization with early release of processors 失效
标题翻译：多处理器串行化与早期版本的处理器
公开(公告)号：US06079013A
公开(公告)日：2000-06-20
申请号：US70429
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F9/52 , G06F9/318 , G06F12/06
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3017
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

4. 发明授权

US6119219A System serialization with early release of individual processor 失效
标题翻译：系统串行化与早期发布的单个处理器
公开(公告)号：US6119219A
公开(公告)日：2000-09-12
申请号：US70595
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F15/177 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3017 , G06F9/3834
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

5. 发明授权

US5713035A Linking program access register number with millicode operand access 失效
标题翻译：将程序访问寄存器编号与millicode操作数访问连接
公开(公告)号：US5713035A
公开(公告)日：1998-01-27
申请号：US414164
申请日：1995-03-31
申请人： Mark Steven Farrell , Barry Watson Krumm , John Stephen Liptay , Charles Franklin Webb , Steven QiHong Ying
发明人： Mark Steven Farrell , Barry Watson Krumm , John Stephen Liptay , Charles Franklin Webb , Steven QiHong Ying
IPC分类号： G06F9/318 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3863
摘要： In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.
摘要翻译：在毫模式处理器中，程序访问寄存器中访问列表条目标记（ALET）的位（0-6）必须为零，以使访问寄存器转换成功。当将ALET从程序访问寄存器复制到一个毫代数据访问寄存器时，写入该程序存取寄存器的ALET位0-3被设置为读取数据的程序访问寄存器的访问寄存器号。这建立了程序访问寄存器编号与可能由millicode尝试的任何逻辑提取之间的亲和度。

6. 发明授权

US5649155A Cache memory accessed by continuation requests 失效
标题翻译：缓存由连续请求访问
公开(公告)号：US5649155A
公开(公告)日：1997-07-15
申请号：US414176
申请日：1995-03-31
申请人： Barry Watson Krumm , Steven Tyler Comfort , Jin Ji , John Stephen Liptay , Charles Franklin Webb , David Man Chow Wong , Steven QiHong Ying
发明人： Barry Watson Krumm , Steven Tyler Comfort , Jin Ji , John Stephen Liptay , Charles Franklin Webb , David Man Chow Wong , Steven QiHong Ying
IPC分类号： G06F9/34 , G06F9/38 , G06F12/08 , G06F12/10 , G06F12/04
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0851 , G06F12/0882 , G06F9/34 , G06F9/383 , G06F12/1054
摘要： In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a line in said cache memory, the bin number and line position identification of the line in the cache memory are saved in a continuation register. Then, subsequently, when data is fetched from the same line, it is fetched by a continuation request wherein the data saved in the continuation register is used to access the cache memory. The continuation registers provide the abbreviated address data for comparison in both PSC (program store compare) and OSC (operand store compare).
摘要翻译：在高速缓冲存储器系统中，连续寄存器被提供给缩写地址数据，以标识从其获取数据的高速缓冲存储器中的行位置。当从所述高速缓冲存储器中的行中取出数据时，高速缓冲存储器中的行的仓号和行位置标识被保存在连续寄存器中。然后，随后，当从相同的行取出数据时，它被继续请求取出，其中保存在连续寄存器中的数据用于访问高速缓冲存储器。继续寄存器提供用于在PSC（程序存储比较）和OSC（操作数存储比较）中进行比较的缩写地址数据。

7. 发明授权

US5790844A Millicode load and test access instruction that blocks interrupts in response to access exceptions 失效
标题翻译： Millicode加载和测试访问指令阻止中断响应访问异常
公开(公告)号：US5790844A
公开(公告)日：1998-08-04
申请号：US829268
申请日：1997-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A special inillicode instruction "Load With Access Test" explicitly detects access exceptions for storage operands while retaining control in the current millicode routine to insure exceptions are handled correctly and with the right priority. The millicode Load With Access Test instruction operates similarly to the ESA/390 Load instruction except that access exception code is set, interrupts are blocked and the serialization is forced to purge the instruction pipeline and reset the pipeline control without redirection of the instruction stream.
摘要翻译：一个特殊的initicode指令“加载访问测试”显式检测存储操作数的访问异常，同时保留当前millicode例程中的控制，以确保正确处理异常并以正确的优先级。除了访问异常代码被设置，中断被阻止并且串行化被强制清除指令流水线并重新设置流水线控制而不重定向指令流之外，Millicode加载与访问测试指令的操作类似于ESA / 390加载指令。

8. 发明授权

US6105126A Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效
标题翻译：地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码
公开(公告)号：US6105126A
公开(公告)日：2000-08-15
申请号：US70359
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/34
CPC分类号： G06F9/355 , G06F9/30185
摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.
摘要翻译：计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令结果放在第六个周期。

9. 发明授权

US5694587A Specialized millicode instructions for test PSW validity, load with access test, and character translation assist 失效
标题翻译：测试PSW有效性的专用millicode指令，访问测试负载和字符翻译辅助
公开(公告)号：US5694587A
公开(公告)日：1997-12-02
申请号：US414154
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.
摘要翻译：在毫模式架构状态下的流水线计算机处理器使用存储在毫通通用寄存器中的掩码测试程序状态字的有效性。掩码表示程序状态字中的位，如果该字有效，则它们将为零。在字中的相应位置的位和掩码中的位之间执行逻辑“与”运算，另外检查字中的至少一个其他位的状态，除了对应定位的位之外的位。

10. 发明授权

US6085313A Computer processor system for executing RXE format floating point instructions 失效
标题翻译：用于执行RXE格式浮点指令的计算机处理器系统
公开(公告)号：US6085313A
公开(公告)日：2000-07-04
申请号：US070198
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145
摘要： A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.RXE instructions can be used for floating point processing and fixed point processing.
摘要翻译：一种计算机处理器系统，具有用于指令的浮点处理器，其在六个周期流水线中被处理，其中在流水线的第一周期之前取出指令文本，并且在所读取的特定指令的第一周期期间对其进行解码，读取基地址（B）和索引（X）寄存器值以用于地址生成。通过将操作代码的扩展置于指令格式的前四个字节之外来扩展RX类型的指令，并且以这样的方式分配操作代码，使得机器可以仅从操作代码的前8位确定，指令的确切格式。指令格式包括ESA / 390指令SS，RR; RX; S; RRE; RI：和新的RXE指令。其中RXE格式的指令在RX格式中在所述指令寄存器中的相同位置具有它们的R1，X2，B2和D2字段，以使处理器仅从操作代码的前8位确定指令为解码的是RXE格式指令和RXE格式指令的寄存器索引扩展，然后将正确的信息写入所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所提取的指令结果放在第六个循环中.RXE指令可用于浮点处理和定点处理。

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