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1. 发明授权

US07770170B2 Blocking local sense synchronization barrier 有权
标题翻译：阻止本地感应同步屏障
公开(公告)号：US07770170B2
公开(公告)日：2010-08-03
申请号：US11180338
申请日：2005-07-12
申请人： John Rector , Jonathan D. Morrison , Neill M. Clift , Arun U. Kishan
发明人： John Rector , Jonathan D. Morrison , Neill M. Clift , Arun U. Kishan
IPC分类号： G06F9/46 , G06F9/45 , G06F13/00 , G06F17/30
CPC分类号： G06F9/52 , G06F9/522 , Y10S707/99938
摘要： A blocking local sense synchronization barrier is provided. The local sense variable is not processor private or global, but truly local to the synchronization barrier function. Safe deletion is provided by making sure the last operation a thread performs on a barrier is a write. Just before returning, threads increment a field that indicates the count of threads that have left the barrier. Blocking is supported such that threads spin for some interval, and when they decide to block, examine and set (if not already set) the indication of whether a thread is blocking that is to be examined by the last thread to arrive at the barrier to determine whether to set an event to release blocking threads.
摘要翻译：提供阻塞的本地感测同步屏障。局部感知变量不是处理器私有的或全局的，而是真正的本地的同步屏障功能。通过确保线程在屏障上执行的最后一个操作是写入来提供安全删除。在返回之前，线程会增加一个字段，指示已经离开屏障的线程数。阻塞被支持，使得线程旋转一段时间，并且当它们决定阻塞，检查和设置（如果尚未设置）时线程是否阻塞的指示被最后线程检查以到达屏障确定是否设置事件以释放阻塞线程。

2. 发明申请

US20080288750A1 Small barrier with local spinning 有权
标题翻译：局部旋转的小障碍
公开(公告)号：US20080288750A1
公开(公告)日：2008-11-20
申请号：US11803457
申请日：2007-05-15
申请人： Neill M. Clift , Arun U. Kishan
发明人： Neill M. Clift , Arun U. Kishan
IPC分类号： G06F9/30
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier with local spinning. The barrier is described as a barrier object having a bit vector embedded as a pointer. If the vector bit is zero, the object functions as a counter; if the vector bit is one, the object operates as a pointer to a stack. The object includes the total number of threads required to rendezvous at the barrier to trigger release of the threads. The object points to a stack block list that describes each thread that has arrived at the barrier. Arriving at the barrier involves reading the top stack block, pushing onto the list a stack block for the thread that just arrived, decrementing the thread count, and spinning on corresponding local memory locations or timing out and blocking. When the last thread arrives at the barrier, the barrier is reset and all threads at the barrier are awakened for the start of the next process.
摘要翻译：当地纺纱的障碍。屏障被描述为具有嵌入作为指针的位向量的屏障对象。如果向量位为零，则该对象用作计数器; 如果向量位为1，则对象作为指向栈的指针。该对象包括在屏障上会合触发线程释放所需的总线程数。对象指向一个堆栈块列表，描述已经到达屏障的每个线程。到达障碍层面是读取顶层堆栈块，向列表中推出刚刚到达的线程的堆栈块，减少线程计数，并旋转相应的本地存储器位置或超时并阻塞。当最后一个线程到达屏障时，屏障被重置，并且屏障处的所有线程都被唤醒以用于下一个进程的开始。

3. 发明申请

US20100017581A1 LOW OVERHEAD ATOMIC MEMORY OPERATIONS 审中-公开
标题翻译：低过零原子内存操作
公开(公告)号：US20100017581A1
公开(公告)日：2010-01-21
申请号：US12176206
申请日：2008-07-18
申请人： Neill M. Clift , Arun U. Kishan
发明人： Neill M. Clift , Arun U. Kishan
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3863
摘要： Embodiments that provide low-overhead restricted memory transactions are disclosed. In accordance with one embodiment, the method includes providing one or more references to processor-specific data that corresponds to a first processor. The method further includes detecting an interrupt to the first processor when the interrupt indicates modification of the one or more references to the processor-specific data during the execution of one or more instructions. The method also includes taking remedial action on the one or more instructions when the interrupt is detected.
摘要翻译：公开了提供低开销受限内存交易的实施例。根据一个实施例，该方法包括向对应于第一处理器的处理器专用数据提供一个或多个引用。所述方法还包括当所述中断指示在执行一个或多个指令期间对所述处理器特定数据的一个或多个引用的修改时，检测到所述第一处理器的中断。该方法还包括当检测到中断时对一个或多个指令采取补救措施。

4. 发明授权

US08060881B2 Small barrier with local spinning 有权
标题翻译：局部旋转的小障碍
公开(公告)号：US08060881B2
公开(公告)日：2011-11-15
申请号：US11803457
申请日：2007-05-15
申请人： Neill M. Clift , Arun U. Kishan
发明人： Neill M. Clift , Arun U. Kishan
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier with local spinning. The barrier is described as a barrier object having a bit vector embedded as a pointer. If the vector bit is zero, the object functions as a counter; if the vector bit is one, the object operates as a pointer to a stack. The object includes the total number of threads required to rendezvous at the barrier to trigger release of the threads. The object points to a stack block list that describes each thread that has arrived at the barrier. Arriving at the barrier involves reading the top stack block, pushing onto the list a stack block for the thread that just arrived, decrementing the thread count, and spinning on corresponding local memory locations or timing out and blocking. When the last thread arrives at the barrier, the barrier is reset and all threads at the barrier are awakened for the start of the next process.
摘要翻译：当地纺纱的障碍。屏障被描述为具有嵌入作为指针的位向量的屏障对象。如果向量位为零，则该对象用作计数器; 如果向量位为1，则对象作为指向栈的指针。该对象包括在屏障上会合触发线程释放所需的总线程数。对象指向一个堆栈块列表，描述已经到达屏障的每个线程。到达障碍层面是读取顶层堆栈块，向列表中推出刚刚到达的线程的堆栈块，减少线程计数，并旋转相应的本地存储器位置或超时并阻塞。当最后一个线程到达屏障时，屏障被重置，并且屏障处的所有线程都被唤醒以用于下一个进程的开始。

5. 发明授权

US08832411B2 Working set swapping using a sequentially ordered swap file 有权
标题翻译：使用顺序排序的交换文件进行工作集交换
公开(公告)号：US08832411B2
公开(公告)日：2014-09-09
申请号：US13326182
申请日：2011-12-14
申请人： Mehmet Iyigun , Yevgeniy Bak , Landy Wang , Arun U. Kishan
发明人： Mehmet Iyigun , Yevgeniy Bak , Landy Wang , Arun U. Kishan
IPC分类号： G06F12/02
CPC分类号： G06F12/1009 , G06F12/08 , G06F12/12 , G06F2212/657
摘要： Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.
摘要翻译：所描述的技术使得能够通过使用大量写入和从第二存储器中顺序排序的位置读取页面来有效地交换存储器页面到工作页面的工作集合。当将进程的工作集中的页面写入辅助存储时，可以根据虚拟地址顺序或其他顺序将页面写入专用交换文件中的保留的连续位置。这种写入顺序排列的位置使得能够读取大的，连续的存储器块中的页面簇，从而提供更有效的读取操作以将页面返回到物理存储器。

6. 发明申请

US20130061249A1 DECOUPLING BACKGROUND WORK AND FOREGROUND WORK 有权
公开(公告)号：US20130061249A1
公开(公告)日：2013-03-07
申请号：US13224168
申请日：2011-09-01
申请人： James A. Schwartz, JR. , Arun U. Kishan , Richard K. Neves , David B. Probert , Hari Pulapaka , Alain F. Gefflaut
发明人： James A. Schwartz, JR. , Arun U. Kishan , Richard K. Neves , David B. Probert , Hari Pulapaka , Alain F. Gefflaut
IPC分类号： G06F9/445
CPC分类号： G06F9/542 , G06F9/445 , G06F9/44521 , G06F9/4881 , G06F2209/543
摘要： Systems, methods, and apparatus for separately loading and managing foreground work and background work of an application. In some embodiments, a method is provided for use by an operating system executing on at least one computer. The operating system may identify at least one foreground component and at least one background component of an application, and may load the at least one foreground component for execution separately from the at least one background component. For example, the operating system may execute the at least one foreground component without executing the at least one background component. In some further embodiments, the operating system may use a specification associated with the application to identify at least one piece of computer executable code implementing the at least one background component.

7. 发明申请

US20090187784A1 FAIR AND DYNAMIC CENTRAL PROCESSING UNIT SCHEDULING 有权
标题翻译：公平和动态中央处理单元调度
公开(公告)号：US20090187784A1
公开(公告)日：2009-07-23
申请号：US12016869
申请日：2008-01-18
申请人： Ara Bernardi , Costin Hagiu , NK Srinivas , Ashwin Palekar , Arun U. Kishan , Karthik Thirumalai
发明人： Ara Bernardi , Costin Hagiu , NK Srinivas , Ashwin Palekar , Arun U. Kishan , Karthik Thirumalai
IPC分类号： G06F1/04
CPC分类号： G06F9/5061 , G06F9/4881 , G06F2209/483 , G06F2209/5012 , G06F2209/508
摘要： Embodiments that facilitate the fair and dynamic distribution of central processing unit (CPU) time are disclosed. In accordance with one embodiment, a method includes organizing one or more processes into one or more groups. The method further includes allocating a CPU time interval for each group. The allocation of a CPU time interval for each group is accomplished by equally distributing a CPU cycle based on the number of groups. The method also includes adjusting the allocated CPU time intervals based on a change in the quantity of the one or more groups.
摘要翻译：公开了促进中央处理单元（CPU）时间的公平和动态分配的实施例。根据一个实施例，一种方法包括将一个或多个过程组织成一个或多个组。该方法还包括为每个组分配CPU时间间隔。每个组的CPU时间间隔的分配通过基于组的数量均等地分配CPU周期来实现。该方法还包括基于一个或多个组的数量的改变来调整分配的CPU时间间隔。

8. 发明授权

US09003215B2 Power-aware thread scheduling and dynamic use of processors 有权
标题翻译：电源感知线程调度和处理器的动态使用
公开(公告)号：US09003215B2
公开(公告)日：2015-04-07
申请号：US13214545
申请日：2011-08-22
申请人： Allen Marshall , Andrew J. Ritz , Yimin Deng , Nicholas S. Judge , Arun U. Kishan
发明人： Allen Marshall , Andrew J. Ritz , Yimin Deng , Nicholas S. Judge , Arun U. Kishan
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/5033 , G06F9/5094 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/24 , Y02D50/20
摘要： Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy.
摘要翻译：公开了用于提供功率感知线程调度和处理器的动态使用的技术和设备。在某些方面，监控多核系统以确定核心活动。核心活动可以与将节电计划与性能计划进行平衡的电力政策进行比较。响应于比较可以停放一个或多个核，以减少多核系统的功耗。在另外的方面，可以在预定间隔期间执行功率感知调度以动态地驻留或解除核心。另外的方面包括响应于核心活动和电力政策的比较来调整未标记核心的功率状态。

9. 发明授权

US08321874B2 Intelligent context migration for user mode scheduling 有权
标题翻译：智能上下文迁移用于用户模式调度
公开(公告)号：US08321874B2
公开(公告)日：2012-11-27
申请号：US12242566
申请日：2008-09-30
申请人： Ajith Jayamohan , Arun U. Kishan , Dave Probert , Pedro Teixeira
发明人： Ajith Jayamohan , Arun U. Kishan , Dave Probert , Pedro Teixeira
IPC分类号： G06F9/40
CPC分类号： G06F9/461 , G06F9/545
摘要： Performing directed switches between user mode schedulable (UMS) threads and primary threads enable proper execution of the UMS threads. A primary thread user portion is switched to a UMS thread user portion so that the UMS thread user portion is executed in user mode via the primary thread user portion. The primary thread is then transferred into kernel mode via an implicit switch. A kernel portion of the UMS thread is then executed in kernel mode using the context information of a primary thread kernel portion.
摘要翻译：在用户模式可调度（UMS）线程和主线程之间执行定向切换可以正确执行UMS线程。主线程用户部分被切换到UMS线程用户部分，使得UMS线程用户部分经由主线程用户部分以用户模式执行。然后，主线程通过隐式交换机转移到内核模式。然后使用主线程内核部分的上下文信息在内核模式下执行UMS线程的内核部分。

10. 发明申请

US20110307730A1 Power-Aware Thread Scheduling and Dynamic Use of Processors 有权
标题翻译：强大的线程调度和处理器的动态使用
公开(公告)号：US20110307730A1
公开(公告)日：2011-12-15
申请号：US13214545
申请日：2011-08-22
申请人： Allen Marshall , Yimin Deng , Nicholas S. Judge , Arun U. Kishan , Andrew J. Ritz
发明人： Allen Marshall , Yimin Deng , Nicholas S. Judge , Arun U. Kishan , Andrew J. Ritz
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/5033 , G06F9/5094 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/24 , Y02D50/20
摘要： Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy.
摘要翻译：公开了用于提供功率感知线程调度和处理器的动态使用的技术和设备。在某些方面，监控多核系统以确定核心活动。核心活动可以与将节电计划与性能计划进行平衡的电力政策进行比较。响应于比较可以停放一个或多个核，以减少多核系统的功耗。在另外的方面，可以在预定间隔期间执行功率感知调度以动态地驻留或解除核心。另外的方面包括响应于核心活动和电力政策的比较来调整未标记核心的功率状态。

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