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    • 3. 发明授权
    • Semiconductor devices including fine pitch arrays with staggered contacts
    • 包括具有交错接触的细间距阵列的半导体器件
    • US07960797B2
    • 2011-06-14
    • US11511541
    • 2006-08-29
    • John K. LeeHyuntae KimRichard L. StocksLuan Tran
    • John K. LeeHyuntae KimRichard L. StocksLuan Tran
    • H01L23/528
    • H01L21/76816H01L27/10888H01L2924/0002H01L2924/00
    • A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact that is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.
    • 半导体器件结构包括交错的触点,以促进有源器件区域和导电线之间的小间距,同时最小化触点制造期间的未对准中的一个或两个以及触点的部分之间的接触电阻。 一行的触点与每个其他有源器件区域通信,并且相对于与剩余的有源器件区域通信的另一行的触点交错。 每个接触件可以包括具有相对大的上表面的相对较大的接触塞,以提供相对大量的公差作为用于形成的接触件的上部的接触孔。 在双镶嵌工艺中,接触孔可以与用于诸如位线的导电迹线的沟槽基本上同时形成。 还公开了中间结构,以及用于设计半导体器件结构的方法。
    • 4. 发明申请
    • Semiconductor devices including fine pitch arrays with staggered contacts and methods for designing and fabricating the same
    • 半导体器件包括具有交错接触的细间距阵列和用于设计和制造它们的方法
    • US20080054483A1
    • 2008-03-06
    • US11511541
    • 2006-08-29
    • John K. LeeHyuntae KimRichard L. StocksLuan Tran
    • John K. LeeHyuntae KimRichard L. StocksLuan Tran
    • H01L23/48
    • H01L21/76816H01L27/10888H01L2924/0002H01L2924/00
    • A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.
    • 半导体器件结构包括交错的触点,以促进有源器件区域和导电线之间的小间距,同时最小化触点制造期间的未对准中的一个或两个以及触点的部分之间的接触电阻。 一行的触点与每个其他有源器件区域通信,并且相对于与剩余的有源器件区域通信的另一行的触点交错。 每个接触件可以包括具有相对大的上表面的相对较大的接触塞,以提供相对较大的容许量,因为形成了用于接触的上部的接触孔。 在双镶嵌工艺中,接触孔可以与用于诸如位线的导电迹线的沟槽基本上同时形成。 还公开了中间结构,以及用于设计半导体器件结构的方法。