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1. 发明申请

US20050023693A1 Reliable low-k interconnect structure with hybrid dielectric 有权
标题翻译：具有混合电介质的可靠的低k互连结构
公开(公告)号：US20050023693A1
公开(公告)日：2005-02-03
申请号：US10901868
申请日：2004-07-29
申请人： John Fitzsimmons , Stephen Greco , Jia Lee , Stephen Gates , Terry Spooner , Matthew Angyal , Habib Hichri , Theordorus Standaert , Glenn Biery
发明人： John Fitzsimmons , Stephen Greco , Jia Lee , Stephen Gates , Terry Spooner , Matthew Angyal , Habib Hichri , Theordorus Standaert , Glenn Biery
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.
摘要翻译：公开了一种具有混合电介质的高级后端（BEOL）互连结构。用于通孔电平的层间电介质（ILD）优选地不同于线路电平的ILD。在优选实施例中，通孔级ILD由低k SiCOH材料形成，并且线级ILD由低k聚合物热固性材料形成。

2. 发明申请

US20060043590A1 MAINTAINING UNIFORM CMP HARD MASK THICKNESS 有权
标题翻译：维持均匀的CMP硬掩模厚度
公开(公告)号：US20060043590A1
公开(公告)日：2006-03-02
申请号：US10711145
申请日：2004-08-27
申请人： Steven Shyng-Tsong Chen , Kaushik Kumar , Stephen Greco , Shom Ponoth , Terry Spooner , David Rath , Wei-Tsu Tseng
发明人： Steven Shyng-Tsong Chen , Kaushik Kumar , Stephen Greco , Shom Ponoth , Terry Spooner , David Rath , Wei-Tsu Tseng
IPC分类号： H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/31 , H01L21/469
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.
摘要翻译：化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

3. 发明授权

US06784105B1 Simultaneous native oxide removal and metal neutral deposition method 有权
标题翻译：同时自然氧化物去除和金属中性沉积法
公开(公告)号：US06784105B1
公开(公告)日：2004-08-31
申请号：US10410496
申请日：2003-04-09
申请人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
发明人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
摘要翻译：提供一种制造具有电介质结构的半导体器件的方法，其中使用光刻和蚀刻技术在单个淀积室内使互连结构任意地图案化。在溅射蚀刻工艺之前，电介质结构可任选地被扩散阻挡材料覆盖。该溅射蚀刻工艺用于去除下面的金属导体表面上的自然氧化物，并且包括具有同时沉积金属中性的定向气体轰击。扩散阻挡材料也可以沉积到图案中。

4. 发明申请

US20080026567A1 INCREASING ELECTROMIGRATION LIFETIME AND CURRENT DENSITY IN IC USING VERTICALLY UPWARDLY EXTENDING DUMMY VIA 失效
标题翻译：使用垂直延伸的直流电源增加IC中的电寿命和电流密度
公开(公告)号：US20080026567A1
公开(公告)日：2008-01-31
申请号：US11869044
申请日：2007-10-09
申请人： Stephen Greco , Chao-Kun Hu , Paul McLaughlin
发明人： Stephen Greco , Chao-Kun Hu , Paul McLaughlin
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.
摘要翻译：公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电线。每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

5. 发明申请

US20050242442A1 Customizing back end of the line interconnects 失效
标题翻译：定制线路互连的后端
公开(公告)号：US20050242442A1
公开(公告)日：2005-11-03
申请号：US10835953
申请日：2004-04-30
申请人： Nancy Greco , Stephen Greco , Erik Hedberg
发明人： Nancy Greco , Stephen Greco , Erik Hedberg
IPC分类号： H01L21/44 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76895 , H01L24/05 , H01L2224/05624 , H01L2924/12042 , H01L2924/14 , H01L2924/01029 , H01L2924/00
摘要： Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.
摘要翻译：在最后一个镶嵌布线层次中的铜线对之间的定制连接是通过在覆盖的绝缘层中形成开口，跨越两条线的部分之间的距离，然后用铝填充开口。可以通过用于图案化绝缘层的正性光致抗蚀剂的第二次无掩模UV激光曝光来创建（或完成）开口。如果不产生开口，则覆盖绝缘层的铝连接形状将不会影响两条电线之间的连接。通过用于图案化铝层的抗蚀剂的激光曝光可以实现类似的结果，从而当期望不连接时会导致连接形状的断裂。

6. 发明申请

US20070032055A1 DRY ETCHBACK OF INTERCONNECT CONTACTS 有权
标题翻译：干预互连联系人
公开(公告)号：US20070032055A1
公开(公告)日：2007-02-08
申请号：US11161538
申请日：2005-08-08
申请人： Theodorus Standaert , William Brearley , Stephen Greco , Sujatha Sankaran
发明人： Theodorus Standaert , William Brearley , Stephen Greco , Sujatha Sankaran
IPC分类号： H01L21/20
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/32136 , H01L21/76847 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
摘要翻译：具有降低的接触电阻和改善的可靠性的复合螺柱接触界面的方法和结构。使用包含含氟气体的选择性干蚀刻。在M1 RIE工艺过程中或之后，通过部分干法蚀刻钨触点来降低接触电阻。然后在M1衬套/电镀工艺期间将凹陷接触件金属化。钨接触高度在完全成型后减小。

7. 发明申请

US20070087555A1 INCREASING ELECTROMIGRATION LIFETIME AND CURRENT DENSITY IN IC USING VERTICALLY UPWARDLY EXTENDING DUMMY VIA 有权
标题翻译：增加电力寿命和电流密度
公开(公告)号：US20070087555A1
公开(公告)日：2007-04-19
申请号：US11163410
申请日：2005-10-18
申请人： Stephen Greco , Chao-Kun Hu , Paul McLaughlin
发明人： Stephen Greco , Chao-Kun Hu , Paul McLaughlin
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.
摘要翻译：公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电线。每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

8. 发明申请

US20070120232A1 LASER FUSE STRUCTURES FOR HIGH POWER APPLICATIONS 失效
标题翻译：高功率应用的激光保险丝结构
公开(公告)号：US20070120232A1
公开(公告)日：2007-05-31
申请号：US11164640
申请日：2005-11-30
申请人： Stephen Greco , Erik Hedberg , Dae-Young Jung , Paul McLaughlin , Christopher Muzzy , Norman Rohrer , Jean Wynne
发明人： Stephen Greco , Erik Hedberg , Dae-Young Jung , Paul McLaughlin , Christopher Muzzy , Norman Rohrer , Jean Wynne
IPC分类号： H01L23/62
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).
摘要翻译：本发明涉及一种用于大功率应用的激光熔丝结构。具体地，本发明的激光熔丝结构包括第一和第二导电支撑元件（12a，12b），至少一个导电熔丝（14），第一和第二连接元件（20a，20b）和第一和第二金属线（22a，22b）。导电支撑元件（12a，12b），导电可熔连接件（14）和金属线（22A，22b）位于第一金属级（3）处，而连接元件（20a， 20b）位于第二不同的金属层（4）处，并且通过导电通孔叠层（18a，18b）连接到导电支撑元件（12a，12b）和金属线（22a，22b） b，23a，23b），其在第一和第二金属水平面（3,4）之间延伸。

9. 发明申请

US20070164421A1 STRUCTURE TO MONITOR ARCING IN THE PROCESSING STEPS OF METAL LAYER BUILD ON SILICON-ON-INSULATOR SEMICONDUCTORS 失效
标题翻译：金属绝缘子半导体制造金属层加工步骤中的结构监测
公开(公告)号：US20070164421A1
公开(公告)日：2007-07-19
申请号：US11306944
申请日：2006-01-17
申请人： Ishtiaq Ahsan , Christine Bunke , Stephen Greco
发明人： Ishtiaq Ahsan , Christine Bunke , Stephen Greco
IPC分类号： H01L23/52
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.
摘要翻译：本发明通过可以容易地结合在晶片上的检测结构来检测电荷引起的缺陷，以检测半导体处理线的后端处理线路中的电荷引起的损伤。测试宏被设计成将电弧从电荷累积天线结构引导到跨平行板电极的另一电荷累积天线结构。当存在预定足够强度的电弧时，宏将经历可测量的短路电压击穿。平行板电极都可以处于微芯片的浮动电位，以监测CMP诱导或光刻诱发的电荷失效机理，或者将一个电极电连接到地电位结构以捕获电荷引起的损伤，因此具有区别的能力两者之间。

10. 发明申请

US20050200024A1 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US20050200024A1
公开(公告)日：2005-09-15
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
发明人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

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