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1. 发明授权

US07755634B1 System, method and computer program product for branching during programmable vertex processing 有权
标题翻译：可编程顶点处理中的分支的系统，方法和计算机程序产品
公开(公告)号：US07755634B1
公开(公告)日：2010-07-13
申请号：US11286809
申请日：2005-11-22
申请人： John Erik Lindholm , Simon S. Moy , Robert Steven Glanville
发明人： John Erik Lindholm , Simon S. Moy , Robert Steven Glanville
IPC分类号： G09G5/37 , G09G5/36 , G06T1/60
CPC分类号： G06T15/005 , G06T11/40 , G06T15/04 , G06T15/50 , G06T15/503 , G06T15/506
摘要： A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.
摘要翻译：提供了一种系统，方法和计算机程序产品，用于在图形处理期间进行分支。最初，对数据执行第一操作。响应于第一操作，对第二操作执行分支操作。第一操作和第二操作与从预定指令集中选择的指令相关联。

2. 发明授权

US07002588B1 System, method and computer program product for branching during programmable vertex processing 有权
标题翻译：可编程顶点处理中的分支的系统，方法和计算机程序产品
公开(公告)号：US07002588B1
公开(公告)日：2006-02-21
申请号：US10391930
申请日：2003-03-19
申请人： John Erik Lindholm , Simon S. Moy , Robert Steven Glanville
发明人： John Erik Lindholm , Simon S. Moy , Robert Steven Glanville
IPC分类号： G09G5/37 , G09G5/36 , G06T1/60
CPC分类号： G06T15/005 , G06T11/40 , G06T15/04 , G06T15/50 , G06T15/503 , G06T15/506
摘要： A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.
摘要翻译：提供了一种系统，方法和计算机程序产品，用于在图形处理期间进行分支。最初，对数据执行第一操作。响应于第一操作，对第二操作执行分支操作。第一操作和第二操作与从预定指令集中选择的指令相关联。

3. 发明申请

US20100122067A1 ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR 审中-公开
标题翻译：多功能微处理器中的交叉螺纹指令分配
公开(公告)号：US20100122067A1
公开(公告)日：2010-05-13
申请号：US12690225
申请日：2010-01-20
申请人： John Erik Lindholm , Brett Coon , Simon S. Moy
发明人： John Erik Lindholm , Brett Coon , Simon S. Moy
IPC分类号： G06F9/312
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
摘要翻译：诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。如果有多个功能单元可用，则可以并行调度多个指令。

4. 发明授权

US07676657B2 Across-thread out-of-order instruction dispatch in a multithreaded microprocessor 有权
标题翻译：在多线程微处理器中进行跨线程无序指令调度
公开(公告)号：US07676657B2
公开(公告)日：2010-03-09
申请号：US11548272
申请日：2006-10-10
申请人： John Erik Lindholm , Brett Coon , Simon S. Moy
发明人： John Erik Lindholm , Brett Coon , Simon S. Moy
IPC分类号： G06F9/00
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
摘要翻译：诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。如果有多个功能单元可用，则可以并行调度多个指令。

5. 发明授权

US07456835B2 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07456835B2
公开(公告)日：2008-11-25
申请号：US11339937
申请日：2006-01-25
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T1/00 , G09G5/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

6. 发明授权

US07864185B1 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07864185B1
公开(公告)日：2011-01-04
申请号：US12256848
申请日：2008-10-23
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T15/20 , G06T1/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

7. 发明申请

US20080143730A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20080143730A1
公开(公告)日：2008-06-19
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

8. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

9. 发明授权

US07310722B2 Across-thread out of order instruction dispatch in a multithreaded graphics processor 有权
标题翻译：在多线程图形处理器中跨线程序指令调度
公开(公告)号：US07310722B2
公开(公告)日：2007-12-18
申请号：US10742514
申请日：2003-12-18
申请人： Simon S. Moy , John Erik Lindholm
发明人： Simon S. Moy , John Erik Lindholm
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions are fetched into an instruction buffer that is configured to store an instruction from each of the threads. A dispatch circuit determines which instructions in the buffer are ready to execute and may issue any ready instruction for execution. An instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched into the buffer first. Once an instruction from a particular thread has issued, the fetch circuit fills the available buffer location with the following instruction from that thread.
摘要翻译：诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。指令被读取到指令缓冲区中，该缓冲器被配置为存储来自每个线程的指令。调度电路确定缓冲器中的哪些指令准备好执行，并且可以发出任何可用的执行指令。无论哪个指令首先被提取到缓冲区，可以在来自另一个线程的指令之前发出来自一个线程的指令。一旦来自特定线程的指令已经发出，则获取电路使用该线程中的以下指令来填充可用的缓冲器位置。

10. 发明授权

US07103720B1 Shader cache using a coherency protocol 有权
标题翻译：着色缓存使用一致性协议
公开(公告)号：US07103720B1
公开(公告)日：2006-09-05
申请号：US10696714
申请日：2003-10-29
申请人： Simon S. Moy , John Erik Lindholm
发明人： Simon S. Moy , John Erik Lindholm
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0875 , G06T15/10
摘要： Methods and systems for caching graphics data using dedicated level one caches and a shared level two cache are described. Furthermore, each method includes a protocol for maintaining coherency between the level one caches and between the level one caches and the level two cache. The level one caches may store different versions of the graphics data, permitting simultaneous processing of execution threads, each thread accessing a different version of the graphics data.
摘要翻译：描述使用专用一级高速缓存和共享二级缓存来缓存图形数据的方法和系统。此外，每个方法包括用于维持一级高速缓存之间以及一级高速缓存与二级高速缓存之间的一致性的协议。一级缓存可以存储图形数据的不同版本，允许执行线程的同时处理，每个线程访问不同版本的图形数据。

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