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    • 7. 发明授权
    • Overrunning clutch
    • 超速离合器
    • US07341135B2
    • 2008-03-11
    • US11557042
    • 2006-11-06
    • Feng Jin
    • Feng Jin
    • F16D41/12
    • F16D41/12
    • An overrunning clutch comprising a ratchet wheel (1) and a plurality of pawls (2) is disclosed. Each of the pawls (2) is rotationally supported on a disk member (5) by a shaft (3). The clutch is characterized by a permanent magnet (4) being fixed on the disk member (5) between the axes of the disk member (5) and the shaft (3) and facing the tail end of each pawl (2). Because each of the pawls are not driven by a spring in the clutch, the clutch could not be malfunction due to the fatigue failure of the spring in the case of frequent heavy load.
    • 公开了一种包括棘轮(1)和多个棘爪(2)的超越离合器。 每个棘爪(2)通过轴(3)旋转地支撑在盘构件(5)上。 离合器的特征在于,在盘构件(5)和轴(3)的轴线之间并面对每个棘爪(2)的尾端的永久磁铁(4)固定在盘构件(5)上。 因为每个棘爪不是由离合器中的弹簧驱动的,所以在频繁重载的情况下由于弹簧的疲劳破坏,离合器不能发生故障。
    • 10. 发明授权
    • Method for making integrated circuits including features with a relatively small critical dimension
    • 制造集成电路的方法,包括具有相对小的临界尺寸的特征
    • US06322934B1
    • 2001-11-27
    • US09409115
    • 1999-09-30
    • John David CuthbertFeng Jin
    • John David CuthbertFeng Jin
    • G03F900
    • G03F7/70466G03F7/2022
    • A method is for making an integrated circuit on a semiconductor wafer, where the integrated circuit includes circuit features having a desired, relatively small, critical dimension. The method preferably comprises the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension. The designing step preferably includes determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift. The method preferably includes steps of fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps. The present invention recognizes that the scaling factor is not a single number, but instead is a non-linear function which is also based upon the shift between exposure steps.
    • 一种用于在半导体晶片上制造集成电路的方法,其中集成电路包括具有期望的,相对小的临界尺寸的电路特征。 该方法优选地包括以下步骤:设计包括具有临界尺寸的图案特征的掩模版,以形成相应的电路特征,基于由多个曝光步骤之间移动而定义的重叠区域,使得电路特征具有期望的,相对较小的, 关键维度。 设计步骤优选地包括确定缩放因子函数,用于将图案特征的临界尺度和向电路特征的期望临界尺度的偏移相关联,同时考虑到比例因子函数也是该偏移的函数。 该方法优选包括以下步骤:基于多个曝光步骤,制造掩模版并使用掩模版将集成电路制成在半导体晶片上。 本发明认识到缩放因子不是单个数字,而是基于曝光步骤之间的偏移的非线性函数。