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1. 发明授权

US07459923B2 Probe interposers and methods of fabricating probe interposers 失效
标题翻译：探头插入件和制作探针插入件的方法
公开(公告)号：US07459923B2
公开(公告)日：2008-12-02
申请号：US11544360
申请日：2006-10-06
申请人： John Caldwell , Jerry McBride , Brett Crump , Phil Byrd
发明人： John Caldwell , Jerry McBride , Brett Crump , Phil Byrd
IPC分类号： G01R31/02
CPC分类号： G01R1/07307 , G01R3/00 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： The invention includes probe interposers and methods of fabricating pose interposers. In one implementation, a method of fabricating a probe interposer includes providing a substrate having a frontside and a backside. Probe tips are lithographically patterned on the substrate frontside. The probe tips have electrically conductive outer ends configured to mechanically and electrically engage conductive contact surfaces of a circuit substrate to be probed. Mechanical hard stops are lithographically patterned on the substrate frontside. The mechanical hard stops have outer surfaces configured to mechanically engage some surface of the circuit substrate during probe of the circuit substrate with the probe interposer. The invention includes probe interposers independent of method of fabrication.
摘要翻译：本发明包括探针插入件和制造姿势插入件的方法。在一个实施方案中，制造探针插入件的方法包括提供具有前侧和背侧的基底。探针尖端在衬底前方光刻图案化。探针尖端具有导电外端，其被配置为机械地和电接合待探测的电路基板的导电接触表面。机械硬止动件在基板前侧被光刻图案化。机械硬止动件具有外表面，其被配置为在具有探针插入件的电路基板的探针期间机械接合电路基板的某些表面。本发明包括独立于制造方法的探针插入件。

2. 发明申请

US20070236233A1 Probe interposers and methods of fabricating probe interposers 失效
标题翻译：探头插入件和制作探针插入件的方法
公开(公告)号：US20070236233A1
公开(公告)日：2007-10-11
申请号：US11544360
申请日：2006-10-06
申请人： John Caldwell , Jerry McBride , Brett Crump , Phil Byrd
发明人： John Caldwell , Jerry McBride , Brett Crump , Phil Byrd
IPC分类号： G01R31/02
CPC分类号： G01R1/07307 , G01R3/00 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： The invention includes probe interposers and methods of fabricating pose interposers. In one implementation, a method of fabricating a probe interposer includes providing a substrate having a frontside and a backside. Probe tips are lithographically patterned on the substrate frontside. The probe tips have electrically conductive outer ends configured to mechanically and electrically engage conductive contact surfaces of a circuit substrate to be probed. Mechanical hard stops are lithographically patterned on the substrate frontside. The mechanical hard stops have outer surfaces configured to mechanically engage some surface of the circuit substrate during probe of the circuit substrate with the probe interposer. The invention includes probe interposers independent of method of fabrication.
摘要翻译：本发明包括探针插入件和制造姿势插入件的方法。在一个实施方案中，制造探针插入件的方法包括提供具有前侧和背侧的基底。探针尖端在衬底前方光刻图案化。探针尖端具有导电外端，其被配置为机械地和电接合待探测的电路基板的导电接触表面。机械硬止动件在基板前侧被光刻图案化。机械硬止动件具有外表面，其被配置为在具有探针插入件的电路基板的探针期间机械接合电路基板的某些表面。本发明包括独立于制造方法的探针插入件。

3. 发明申请

US20070245552A1 Probe interposers and methods of fabricating probe interposers 审中-公开
公开(公告)号：US20070245552A1
公开(公告)日：2007-10-25
申请号：US11400583
申请日：2006-04-07
申请人： John Caldwell , Jerry McBride , Brett Crump , Phil Byrd
发明人： John Caldwell , Jerry McBride , Brett Crump , Phil Byrd
IPC分类号： H01L21/302 , H05K3/36
CPC分类号： G01R1/07307 , G01R3/00 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： The invention includes probe interposers and methods of fabricating pose interposers. In one implementation, a method of fabricating a probe interposer includes providing a substrate having a frontside and a backside. Probe tips are lithographically patterned on the substrate frontside. The probe tips have electrically conductive outer ends configured to mechanically and electrically engage conductive contact surfaces of a circuit substrate to be probed. Mechanical hard stops are lithographically patterned on the substrate frontside. The mechanical hard stops have outer surfaces configured to mechanically engage some surface of the circuit substrate during probe of the circuit substrate with the probe interposer. The invention includes probe interposers independent of method of fabrication.

4. 发明申请

US20050262405A1 Apparatus and method for reducing test resources in testing DRAMs 审中-公开
标题翻译：用于降低测试DRAM测试资源的装置和方法
公开(公告)号：US20050262405A1
公开(公告)日：2005-11-24
申请号：US11188932
申请日：2005-07-25
申请人： Chris Cooper , Siang Giam , Jerry McBride , Scott Gatzemeier , Scott Ayres , David Brown
发明人： Chris Cooper , Siang Giam , Jerry McBride , Scott Gatzemeier , Scott Ayres , David Brown
IPC分类号： G01R31/02 , G11C29/00 , G11C29/26 , G11C29/40 , G11C29/48
CPC分类号： G11C29/006 , G01R31/31932 , G11C11/401 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/26 , G11C29/40 , G11C29/48 , G11C29/56 , G11C2029/5602
摘要： An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
摘要翻译：公开了一种用于减小在芯片在半导体晶片上测试计算机存储器件，特别是Rambus DRAM所需的引脚驱动器计数的装置和方法。通过减少引脚数量，可以同时测试更多的DRAM，从而降低测试成本和时间。一个优选实施例利用预充电时钟的后沿选择新的活动存储体地址，使得选择新的活动地址所需的地址线不必与行线同时被访问。

5. 发明申请

US20070168790A1 Apparatus and method for reducing test resources in testing drams 审中-公开
标题翻译：用于降低测试中测试资源的装置和方法
公开(公告)号：US20070168790A1
公开(公告)日：2007-07-19
申请号：US11445944
申请日：2006-06-02
申请人： Chris Cooper , Siang Giam , Jerry McBride , Scott Gatzemeier , Scott Ayres , David Brown
发明人： Chris Cooper , Siang Giam , Jerry McBride , Scott Gatzemeier , Scott Ayres , David Brown
IPC分类号： G01R31/28
CPC分类号： G11C29/006 , G01R31/31932 , G11C11/401 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/26 , G11C29/40 , G11C29/48 , G11C29/56 , G11C2029/5602
摘要： An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
摘要翻译：公开了一种用于减小在芯片在半导体晶片上测试计算机存储器件，特别是Rambus DRAM所需的引脚驱动器计数的装置和方法。通过减少引脚数量，可以同时测试更多的DRAM，从而降低测试成本和时间。一个优选实施例利用预充电时钟的后沿选择新的活动库地址，使得选择新的活动地址所需的地址线不必与行线同时被访问。

6. 发明申请

US20060156136A1 System for storing device test information on a semiconductor device using on-device logic for determination of test results 审中-公开
标题翻译：用于在半导体器件上存储器件测试信息的系统，使用用于确定测试结果的器件逻辑
公开(公告)号：US20060156136A1
公开(公告)日：2006-07-13
申请号：US11357487
申请日：2006-02-17
申请人： Jerry McBride
发明人： Jerry McBride
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/2894 , G01R31/31703 , G01R31/31718 , G11C16/04 , G11C29/38 , G11C29/44 , G11C29/56 , G11C2029/1208
摘要： A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on the semiconductor device and are subsequently stored in nonvolatile memory elements. The invention eliminates the need for device testing equipment to perform a determination of test results and thus may simplify the design of test equipment. In one embodiment of the invention, passing test results are stored in a mixed code of set and unset nonvolatile memory elements such that the test results contain information about correct application of test signals as well as correct functioning of the semiconductor device.
摘要翻译：一种用于测试半导体器件并将测试结果存储在被测设备上的非易失性存储器元件的系统，其中半导体器件包括允许在器件上确定测试结果的逻辑电路。测试结果临时存储在半导体器件上的一个或多个锁存元件中，随后存储在非易失性存储元件中。本发明消除了对设备测试设备执行测试结果的确定的需要，从而可以简化测试设备的设计。在本发明的一个实施例中，通过测试结果存储在设置和非设置非易失性存储器元件的混合代码中，使得测试结果包含有关测试信号的正确应用以及半导体器件的正确功能的信息。

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