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1. 发明申请

US20060170079A1 Integrated circuit device having encapsulant dam with chamfered edge 审中-公开
标题翻译：具有倒角边缘的密封剂坝的集成电路装置
公开(公告)号：US20060170079A1
公开(公告)日：2006-08-03
申请号：US11048968
申请日：2005-02-02
申请人： John Brennan , Patrick Carberry , Joseph Freund , George Libricz , Ralph Moyer
发明人： John Brennan , Patrick Carberry , Joseph Freund , George Libricz , Ralph Moyer
IPC分类号： H01L23/495
CPC分类号： H01L23/047 , H01L23/24 , H01L23/49861 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L2223/6611 , H01L2223/6644 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2224/78313 , H01L2224/85181 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit device is provided having a substrate, at least one integrated circuit element and a leadframe. The integrated circuit element and the leadframe are disposed on the substrate. The leadframe has at least one lead and at least one encapsulant dam disposed on the at least one lead. The encapsulant dam has at least one chamfered edge to provide clearance for a wire feed during a wire-bonding process.
摘要翻译：提供了具有基板，至少一个集成电路元件和引线框架的集成电路器件。集成电路元件和引线框架设置在基板上。引线框具有至少一个引线和至少一个密封剂坝，其设置在至少一个引线上。密封剂坝具有至少一个倒角边缘，以在引线接合过程期间为焊丝进给提供间隙。

2. 发明申请

US20060145317A1 Leadframe designs for plastic cavity transistor packages 审中-公开
标题翻译：引线框设计用于塑料腔晶体管封装
公开(公告)号：US20060145317A1
公开(公告)日：2006-07-06
申请号：US11029254
申请日：2004-12-31
申请人： John Brennan , Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer , John Osenbach
发明人： John Brennan , Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer , John Osenbach
IPC分类号： H01L21/44 , H01L23/495
CPC分类号： H01L23/49861 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The specification describes a plastic cavity package for semiconductor devices that provides additional mechanical integrity for leads that extend from the plastic housing. Portions of the leads that are within the plastic housing are provided with cutouts. When the plastic housing is formed, or when the cavity is filled with polymer, plastic material fills the cutout, and joins to the mass of plastic on either side of the cutout, thus forming a continuous integral mass of plastic. The end result is that the plastic in the cutout, coupled to the main plastic mass, and to the rigid package sidewall, forms an effective anchor against pulling and bending forces the leads may encounter in manufacture or use.
摘要翻译：本说明书描述了一种用于半导体器件的塑料腔封装，为从塑料外壳延伸的引线提供额外的机械完整性。在塑料外壳内的引线部分设有切口。当塑料壳体形成时，或者当空腔填充聚合物时，塑料材料填充切口，并且连接到切口两侧的塑料块，从而形成连续的整体塑料块。最终的结果是，连接到主塑料块的切口中的塑料和刚性的包装侧壁形成了有效的锚固件，以防止引线在制造或使用中遇到的拉力和弯曲力。

3. 发明申请

US20070241433A1 Semiconductor device package with base features to reduce leakage 有权
标题翻译：半导体器件封装具有基极特性，可减少泄漏
公开(公告)号：US20070241433A1
公开(公告)日：2007-10-18
申请号：US11788346
申请日：2007-04-19
申请人： Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer , John Osenbach , Hugo Safar , Thomas Shilling
发明人： Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer , John Osenbach , Hugo Safar , Thomas Shilling
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/4334 , H01L23/49541 , H01L23/49861 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/14 , H01L2924/16195 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.
摘要翻译：半导体器件封装包括包括基底和侧壁的容器。基座被配置为支撑半导体器件芯片，并且引线框架延伸穿过至少一个侧壁。引导框架在侧壁内的一部分具有穿透引线框架的至少一个孔。侧壁材料延伸到孔中，从而形成强界面结合，其提供低泄漏侧壁引线框架界面。底座具有位于至少一个侧壁的厚度内并与至少一个侧壁接合的折入特征，从而形成低泄漏的底壁 - 侧壁界面。基座的顶表面具有凹槽，该凹槽位于至少一个侧壁的厚度内并与至少一个侧壁接合，由此增强了低泄漏的底壁 - 侧壁界面。

4. 发明申请

US20060131707A1 Semiconductor device package with reduced leakage 有权
标题翻译：半导体器件封装减少泄漏
公开(公告)号：US20060131707A1
公开(公告)日：2006-06-22
申请号：US11015534
申请日：2004-12-18
申请人： Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer , John Osenbach , Hugo Safar , Thomas Shilling
发明人： Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer , John Osenbach , Hugo Safar , Thomas Shilling
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/4334 , H01L23/49541 , H01L23/49861 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/14 , H01L2924/16195 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage-base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.
摘要翻译：半导体器件封装包括包括基底和侧壁的容器。基座被配置为支撑半导体器件芯片，并且引线框架延伸穿过至少一个侧壁。引导框架在侧壁内的一部分具有穿透引线框架的至少一个孔。侧壁材料延伸到孔中，从而形成强界面结合，其提供低泄漏侧壁引线框架界面。底座具有位于至少一个侧壁的厚度内的折入特征，并与至少一个侧壁接合，从而形成低泄漏基底 - 侧壁界面。基座的顶表面具有凹槽，该凹槽位于至少一个侧壁的厚度内并与至少一个侧壁接合，由此增强了低泄漏的底壁 - 侧壁界面。

5. 发明申请

US20060131704A1 Packages for encapsulated semiconductor devices and method of making same 有权
标题翻译：用于封装半导体器件的封装及其制造方法
公开(公告)号：US20060131704A1
公开(公告)日：2006-06-22
申请号：US11015535
申请日：2004-12-18
申请人： Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer
发明人： Patrick Carberry , Jeffery Gilbert , George Libricz , Ralph Moyer
IPC分类号： H01L23/495
CPC分类号： H01L23/057 , H01L23/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device package comprises a container having a base and side walls of an electrically insulating material. A semiconductor device chip is disposed on the base, and a lead frame extends through the side walls. At least one electrical conductor couples the lead frame to the chip. A first layer of an electrically insulating cured gel covers the chip and the lead frame, and a second layer of an electrically insulating cured gel covers at least the portion of the first layer that covers the chip, but does not extend to the side walls. In one embodiment, the second layer has the shape of a dome. In a preferred embodiment the gel comprises silicone. In another embodiment a third layer of conformal insulating material is disposed on the second layer and essentially fills the container. Also is described is a method of making the package for use with RFLDMOS chips.
摘要翻译：半导体器件封装包括具有电绝缘材料的基底和侧壁的容器。半导体器件芯片设置在基座上，引线框架延伸穿过侧壁。至少一个电导体将引线框架连接到芯片。电绝缘固化凝胶的第一层覆盖芯片和引线框架，并且电绝缘固化凝胶的第二层至少覆盖覆盖芯片的第一层的部分，但不延伸到侧壁。在一个实施例中，第二层具有圆顶的形状。在优选的实施方案中，凝胶包含硅树脂。在另一个实施例中，第三层共形绝缘材料设置在第二层上并基本上填充容器。还描述了制造用于RFLDMOS芯片的封装的方法。

6. 发明申请

US20050146413A1 Electrical devices having adjustable electrical characteristics 有权
标题翻译：具有可调电特性的电器
公开(公告)号：US20050146413A1
公开(公告)日：2005-07-07
申请号：US10746824
申请日：2003-12-24
申请人： Patrick Carberry , Jeffrey Gilbert
发明人： Patrick Carberry , Jeffrey Gilbert
IPC分类号： H01C10/12 , H01F21/02 , H01C10/10
CPC分类号： H01C10/12 , H01F21/02
摘要： Electrical devices having tunable electrical characteristics are provided, such as variable resistors, capacitors and inductors. The tunable electrical characteristics are achieved by placing an appropriate material between substrate layers and by controllably applying a pressure to the material to compress the material or alter the shape of a well in which the material is contained, and thereby alter the electrical characteristics of the electrical device. The composition, shape and dimension of the embedded materials determine how the electrical characteristics of the electrical device are altered upon compression of the embedded material in response to an applied control signal. Generally, as the embedded material is compressed, the material will become more dense and the electrical characteristics of the integrated electrical device is altered.
摘要翻译：提供具有可调电特性的电器件，例如可变电阻器，电容器和电感器。可调谐的电特性是通过在衬底层之间放置适当的材料并且通过可控地向材料施加压力以压缩材料或改变其中所含材料的孔的形状，从而改变电气特性设备。嵌入材料的组成，形状和尺寸决定了如何响应于所施加的控制信号压缩嵌入材料而改变电气装置的电气特性。通常，当嵌入材料被压缩时，材料将变得更致密，并且整合的电气设备的电特性被改变。

7. 发明申请

US20060172456A1 Device packages having stable wirebonds 有权
标题翻译：具有稳定引线键的器件封装
公开(公告)号：US20060172456A1
公开(公告)日：2006-08-03
申请号：US10702875
申请日：2003-11-05
申请人： Brett Campbell , Patrick Carberry , Jason Goodelle , Michael Quinn
发明人： Brett Campbell , Patrick Carberry , Jason Goodelle , Michael Quinn
IPC分类号： H01L21/50 , H01L21/48
CPC分类号： H01L24/85 , H01L24/45 , H01L24/48 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48091 , H01L2224/48137 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/85214 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15173 , H01L2924/20751 , H01L2924/20752 , H01L2224/78 , H01L2924/00 , H01L2924/013 , H01L2224/45099 , H01L2924/00015 , H01L2924/01006 , H01L2224/85399 , H01L2224/05599
摘要： A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in the package, characterized by (c) causing energy from an external source to heat at least one predetermined segment of the wire to a temperature that is below its melting point (MP) but not below its recrystallization temperature (RCT), and (d) cooling the heated segment to a temperature below its RCT [e.g., to room temperature (RT)], thereby to increase the stiffness modulus of the segment. In one embodiment, the external source is a laser whose optical output is absorbed by the segment. In another embodiment, the heated segment is rapidly cooled (i.e., quenched) to RT. In an embodiment suitable for use with IC chips that have a multiplicity of side-by-side wirebonds, apparatus for heating and cooling the segments and/or the IC chips is located on an x-y table, which allows the wirebonds and the apparatus to be scanned sequentially relative to one another. By increasing the stiffness of at least one segment of each wire, our process increases the physical stability of all of the wires and thereby enables finer wires to be utilized in the fabrication of high-density I/O packaged devices.
摘要翻译：一种制造封装的电气装置的方法包括以下步骤：（a）将导线的一端连接到封装中的第一点（例如，第一电节点），以及（b）将导线的另一端连接到包装中的第二点（例如，第二电节点），其特征在于（c）使来自外部源的能量将至少一个预定的导线段加热至低于其熔点（MP）但不低于其再结晶温度（RCT），和（d）将加热段冷却至低于其RCT的温度[例如达到室温（RT）]，从而增加段的刚度模量。在一个实施例中，外部源是其光输出被该段吸收的激光器。在另一个实施方案中，将加热的段快速冷却（即骤冷）至RT。在适用于具有多个并排线圈的IC芯片的实施例中，用于加热和冷却片段和/或IC芯片的装置位于xy台上，其允许线圈和装置为相对于彼此顺序扫描。通过增加每条导线的至少一个部分的刚度，我们的工艺增加了所有导线的物理稳定性，从而使更细的导线可用于制造高密度I / O封装器件。

8. 发明申请

US20060001157A1 METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING USING STACKED BALL BUMPS 有权
标题翻译：使用堆叠式球泡的集成电路球接法的方法和装置
公开(公告)号：US20060001157A1
公开(公告)日：2006-01-05
申请号：US10881191
申请日：2004-06-30
申请人： Patrick Carberry
发明人： Patrick Carberry
IPC分类号： H01L23/48
CPC分类号： H01L24/48 , H01L23/3171 , H01L23/66 , H01L24/05 , H01L24/45 , H01L24/49 , H01L24/85 , H01L2223/6644 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48463 , H01L2224/48464 , H01L2224/48477 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49175 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/00 , H01L2224/85399
摘要： An integrated circuit comprises at least one circuit element having at least one bond site and a passivation layer. The bond site is accessible through an aperture in the passivation layer. At least two ball bumps are disposed at the bond site. A first ball bump is bonded to the bond site, and each additional ball bump is bonded on a previously bonded ball bump so that the height of the ball bumps is greater than the thickness of the passivation layer above the bond site. A ball bond is bonded to an uppermost ball bump and has a wire formed integrally therewith.
摘要翻译：集成电路包括至少一个具有至少一个键位置和钝化层的电路元件。结合位点可通过钝化层中的孔进入。至少两个球凸块设置在粘结部位。第一个球凸点与结合部位结合，并且每个附加的球凸点接合在预先粘合的球凸起上，使得球凸点的高度大于在粘结部位上方的钝化层的厚度。球接合结合到最上面的球凸块并且具有与其一体形成的线。

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