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1. 发明授权

US08589665B2 Instruction set architecture extensions for performing power versus performance tradeoffs 失效
标题翻译：用于执行功率与性能折衷的指令集架构扩展
公开(公告)号：US08589665B2
公开(公告)日：2013-11-19
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译：提供了用于处理数据处理系统的处理器中的指令的机制。这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

2. 发明授权

US08179674B2 Scalable space-optimized and energy-efficient computing system 失效
标题翻译：可扩展的空间优化和节能计算系统
公开(公告)号：US08179674B2
公开(公告)日：2012-05-15
申请号：US12789583
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , H05K7/20
CPC分类号： G06F1/20
摘要： A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
摘要翻译：提供了可扩展的空间优化和节能计算系统。计算系统包括在六排配置中配置的框架的至少一个级别中的多个模块化隔间。计算系统还包括空气入口，空气混合增压室和至少一个风扇。在计算系统中，多个模块化隔间固定在空气入口上方，空气混合气室固定在多个模块化隔间上方，并且至少一个风扇固定在空气混合气室的上方。当至少一个模块被插入多个模块化隔间中的一个时，模块耦合到框架内的背板。

3. 发明申请

US20110292594A1 Scalable Space-Optimized and Energy-Efficient Computing System 失效
标题翻译：可扩展空间优化和节能计算系统
公开(公告)号：US20110292594A1
公开(公告)日：2011-12-01
申请号：US12789583
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： G06F1/20
摘要： A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
摘要翻译：提供了可扩展的空间优化和节能计算系统。计算系统包括在六排配置中配置的框架的至少一个级别中的多个模块化隔间。计算系统还包括空气入口，空气混合增压室和至少一个风扇。在计算系统中，多个模块化隔间固定在空气入口上方，空气混合气室固定在多个模块化隔间上方，并且至少一个风扇固定在空气混合气室的上方。当至少一个模块被插入多个模块化隔间中的一个时，模块耦合到框架内的背板。

4. 发明申请

US20110296149A1 Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs 失效
标题翻译：用于执行电力与性能权衡的指令集架构扩展
公开(公告)号：US20110296149A1
公开(公告)日：2011-12-01
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/318
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译：提供了用于处理数据处理系统的处理器中的指令的机制。这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

5. 发明申请

US20110292597A1 Stackable Module for Energy-Efficient Computing Systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US20110292597A1
公开(公告)日：2011-12-01
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

6. 发明授权

US08358503B2 Stackable module for energy-efficient computing systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US08358503B2
公开(公告)日：2013-01-22
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： H05K7/20
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

7. 发明申请

US20110178652A1 Dynamically Adjusting an Operating State of a Data Processing System Running Under a Power Cap 失效
标题翻译：动态调整在动力帽下运行的数据处理系统的运行状态
公开(公告)号：US20110178652A1
公开(公告)日：2011-07-21
申请号：US12688214
申请日：2010-01-15
申请人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Malcolm S. Ware
发明人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Malcolm S. Ware
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/329 , Y02D10/24
摘要： A mechanism is provided for dynamically power capping one or more units. A power capping mechanism sets a counter value corresponding to an initial energy budget assigned to a unit for a given interval. Responsive to the unit receiving an operation to perform during the given interval, the power capping mechanism decrements the counter value by a decrement value. Responsive to the given interval expiring, the power capping mechanism sends the counter value to a power control loop in the data processing system, receives a new energy budget from the power control loop, and resets the counter value to a value corresponding to the new energy budget assigned to the unit for a next interval.
摘要翻译：提供了用于动态地对一个或多个单元进行功率封装的机制。功率封顶机构设置与给定间隔分配给单元的初始能量预算对应的计数器值。响应于在给定间隔期间接收要执行的操作的单元，功率封顶机构将计数器值递减减量值。响应于给定的时间间隔到期，功率封顶机制将计数器值发送到数据处理系统中的功率控制回路，从功率控制回路接收新的能量预算，并将计数器值重置为对应于新能量的值分配给该单位的下一个间隔的预算。

8. 发明申请

US20110113270A1 Dynamic Voltage and Frequency Scaling (DVFS) Control for Simultaneous Multi-Threading (SMT) Processors 有权
标题翻译：同步多线程（SMT）处理器的动态电压和频率缩放（DVFS）控制
公开(公告)号：US20110113270A1
公开(公告)日：2011-05-12
申请号：US12616833
申请日：2009-11-12
申请人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Freeman L. Rawson, III , Todd J. Rosedahl , Malcolm S. Ware
发明人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Freeman L. Rawson, III , Todd J. Rosedahl , Malcolm S. Ware
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , Y02D10/126
摘要： A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors.
摘要翻译：提供了用于控制与多个处理器相关联的操作参数的机制。数据处理系统中的控制系统确定数据处理系统的使用松弛值。使用松弛值使用一个或多个活动核心计数值和一个或多个松弛核心计数值来确定。控制系统将新的利用度量度计算为完全利用率值和利用率松弛值之间的差异。控制系统确定新的利用度量是否低于预定利用率阈值。响应于新的利用度量低于预定利用率阈值，控制系统降低了多个处理器的频率。

9. 发明授权

US08261112B2 Optimizing power consumption by tracking how program runtime performance metrics respond to changes in operating frequency 失效
标题翻译：通过跟踪程序运行时性能指标如何响应运行频率的变化来优化功耗
公开(公告)号：US08261112B2
公开(公告)日：2012-09-04
申请号：US12330284
申请日：2008-12-08
申请人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Freeman L. Rawson, III , Malcolm S. Ware
发明人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Freeman L. Rawson, III , Malcolm S. Ware
IPC分类号： G06F1/32 , G06F1/26 , G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.
摘要翻译：一种用于优化执行中的执行处理器的功耗的方法，系统和计算机程序产品。该方法包括分别基于在第一和第二操作频率（OF）下测量的第一和第二性能量度值（PMV）来确定第一灵敏度关系（SR）。第一个SR预测一系列OFs的工作负载性能。基于第一个SR和指定的工作负载性能底线确定三分之一。通过执行在第三个OF操作的处理器来测量第三个PMV。然后确定基于第二和第三PMV的第二SR。逻辑上组合第一和第二SR以产生第三SR。基于第三SR，输出第四个OF。

10. 发明申请

US20110296118A1 Dynamic Row-Width Memory 有权
标题翻译：动态行宽内存
公开(公告)号：US20110296118A1
公开(公告)日：2011-12-01
申请号：US12789641
申请日：2010-05-28
申请人： John B. Carter , Karthick Rajamani
发明人： John B. Carter , Karthick Rajamani
IPC分类号： G06F12/00
CPC分类号： G06F13/1678
摘要： A mechanism is provided for dynamic row-width memory. The memory adapts row width to usage based on memory controller and memory management system software control. The mechanism uses an organization and control of memory array access logic. The memory controller may receive an explicit command using existing column address lines or using a command line into the memory controller. In a first option, the memory controller receives a row width and disables the unused columns and turns off the unused sense amps. In a second option, the memory controller receives a row width and adjusts row count, keeping the number of active cells constant. In a third option, the memory controller receives a row width and adjusts a number of banks.
摘要翻译：为动态行宽存储器提供了一种机制。存储器根据存储器控制器和存储器管理系统软件控制来适应行宽使用。该机制使用组织和控制存储器阵列访问逻辑。存储器控制器可以使用现有列地址线或使用命令行来接收显式命令到存储器控制器中。在第一个选项中，存储器控制器接收行宽度并禁用未使用的列，并关闭未使用的检测放大器。在第二个选项中，存储器控制器接收行宽并调整行数，保持活动单元的数量不变。在第三个选项中，存储器控制器接收行宽并调整多个存储区。

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