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    • 3. 发明授权
    • Handling consolidated tickets
    • 处理综合票
    • US08781865B2
    • 2014-07-15
    • US13570977
    • 2012-08-09
    • John A. BivensValentina Salapura
    • John A. BivensValentina Salapura
    • G06Q10/00
    • G06Q10/06
    • Handling problem tickets in a computing environment, in one aspect, may comprise identifying a plurality of tickets generated in the computing environment that are candidates for consolidation. The identifying may be done based on whether the tickets have the same or similar root cause, whether they are generated from virtual machines having same configuration, and/or one or more other criteria. The tickets which are candidates for consolidation may be grouped into a bundled group, and marked as bundled. Resolving a ticket from the bundled group may potentially resolves all tickets from the bundled group.
    • 在一个方面,在计算环境中处理问题票可以包括识别在计算环境中生成的作为合并的候选者的多个票据。 可以基于票据是否具有相同或相似的根本原因来完成识别,无论它们是从具有相同配置的虚拟机生成的,和/或一个或多个其他标准。 作为合并候选人的票可以分组为捆绑组,并标记为捆绑。 从捆绑组中解决故障单可能会解决捆绑组中的所有故障单。
    • 5. 发明申请
    • HANDLING CONSOLIDATED TICKETS
    • 处理综合票
    • US20140039957A1
    • 2014-02-06
    • US13566326
    • 2012-08-03
    • John A. BivensValentina Salapura
    • John A. BivensValentina Salapura
    • G06Q10/06
    • G06Q10/06
    • Handling problem tickets in a computing environment, in one aspect, may comprise identifying a plurality of tickets generated in the computing environment that are candidates for consolidation. The identifying may be done based on whether the tickets have the same or similar root cause, whether they are generated from virtual machines having same configuration, and/or one or more other criteria. The tickets which are candidates for consolidation may be grouped into a bundled group, and marked as bundled. Resolving a ticket from the bundled group may potentially resolves all tickets from the bundled group.
    • 在一个方面,在计算环境中处理问题票可以包括识别在计算环境中生成的作为合并的候选者的多个票据。 可以基于票据是否具有相同或相似的根本原因来完成识别,无论它们是从具有相同配置的虚拟机生成的,和/或一个或多个其他标准。 作为合并候选人的票可以分组为捆绑组,并标记为捆绑。 从捆绑组中解决故障单可能会解决捆绑组中的所有故障单。
    • 7. 发明授权
    • Method and apparatus of capacity learning for computer systems and applications
    • 计算机系统和应用的能力学习方法和装置
    • US07392159B2
    • 2008-06-24
    • US11157090
    • 2005-06-20
    • John A. BivensPeter Yocom
    • John A. BivensPeter Yocom
    • G06F19/00G06F17/40
    • G06F11/3409
    • The present invention provides a method of determining a metric of capacity in computing systems and computer applications. Capacity in this sense refers to the ability of computer systems and computer applications to perform work. Many applications and multi-hop system strategies could benefit from understanding the amount of work a particular system or application is capable of performing. A metric such as this can be very difficult to calculate due to widely varying system hardware, operating system architectures; application behavior/performance, etc. This disclosure describes a method of dynamic capacity estimation which learns the capacity of an application or system with respect to the work asked of the system and the resources used by the application in question.
    • 本发明提供一种确定计算系统和计算机应用中的容量度量的方法。 在这个意义上的能力是指计算机系统和计算机应用程序执行工作的能力。 许多应用程序和多跳系统策略可以从理解特定系统或应用程序能够执行的工作量获益。 由于广泛变化的系统硬件,操作系统架构,这样的度量可能非常难以计算; 应用行为/性能等。本公开描述了一种动态容量估计的方法,其学习应用或系统相对于系统询问的工作的能力以及所讨论的应用所使用的资源的能力。
    • 10. 发明授权
    • Write bandwidth in a memory characterized by a variable write time
    • 将带宽写入以可变写入时间为特征的存储器中
    • US08374040B2
    • 2013-02-12
    • US13034936
    • 2011-02-25
    • John A. BivensMichele M. FranceschiniLuis A. Lastras-Montano
    • John A. BivensMichele M. FranceschiniLuis A. Lastras-Montano
    • G11C7/00
    • G11C7/1012G06F2213/0038G11C13/0004G11C13/0069G11C2013/008
    • A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
    • 一种存储器系统,其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中,并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时,写入命令完成。