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1. 发明授权

US07436694B2 Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US07436694B2
公开(公告)日：2008-10-14
申请号：US11444295
申请日：2006-05-31
申请人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
发明人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译：具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流连接在第二电阻和工作电位之间的减少元件。

2. 发明申请

US20070047292A1 Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US20070047292A1
公开(公告)日：2007-03-01
申请号：US11444295
申请日：2006-05-31
申请人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
发明人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译：具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流连接在第二电阻和工作电位之间的减少元件。

3. 发明授权

US07400526B2 Memory element, memory read-out element and memory cell 失效
标题翻译：存储元件，存储器读出元件和存储单元
公开(公告)号：US07400526B2
公开(公告)日：2008-07-15
申请号：US11427337
申请日：2006-06-28
申请人： Tim Schoenauer , Michael Kund , Thomas Niedermeier , Joerg Berthold
发明人： Tim Schoenauer , Michael Kund , Thomas Niedermeier , Joerg Berthold
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译：存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换成第一状态状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时，电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流电阻元件的第二端子，以便将电阻元件转换成第二端子状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。

4. 发明申请

US20080055126A1 PARALLELIZATION OF SERIAL DIGITAL INPUT SIGNALS 审中-公开
标题翻译：串行数字输入信号的并行化
公开(公告)号：US20080055126A1
公开(公告)日：2008-03-06
申请号：US11851129
申请日：2007-09-06
申请人： Chaitanya Dudha , Tim Schoenauer , Paul Wallner
发明人： Chaitanya Dudha , Tim Schoenauer , Paul Wallner
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A device configured to parallelize N serial digital input signals includes at least M bit storage devices configured to each respectively store one bit of the N serial digital input signals and provide the one stored bit as a bit of a parallel digital output signal with a bit width M. M is greater than N and N is greater than 1. Symbols with a bit width M are transmitted via the N serial digital input signals such that each of the N serial digital input signals transmits a fraction of the respective symbol. A control device is configured to drive the plurality of bit storage devices cyclically such that at least M bits of the serial digital input signals, which belong to one symbol, are stored in the bit storage devices within a cycle.
摘要翻译：被配置为并行N个串行数字输入信号的设备包括至少M位存储设备，其被配置为分别存储N个串行数字输入信号的一位，并将一个存储的位作为并行数字输出信号的比特宽度 M.M大于N且N大于1.具有位宽M的符号通过N个串行数字输入信号传输，使得N个串行数字输入信号中的每一个发送相应符号的一部分。控制装置被配置为循环地驱动多个位存储装置，使得属于一个符号的串行数字输入信号的至少M位在一个周期内存储在位存储装置中。

5. 发明授权

US07359232B2 Multi-context memory cell 有权
标题翻译：多上下文存储单元
公开(公告)号：US07359232B2
公开(公告)日：2008-04-15
申请号：US11427336
申请日：2006-06-28
申请人： Thomas Niedermeier , Tim Schoenauer
发明人： Thomas Niedermeier , Tim Schoenauer
IPC分类号： G11C7/00
CPC分类号： G11C7/24 , G11C7/1006 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C14/009 , G11C2213/74
摘要： The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.
摘要翻译：多上下文存储单元包括用于存储数据信息项的第一存储器装置和多个第二存储器装置，存储在第一存储器装置中的数据信息可以被保存在每个第二存储器装置中。此外，存储单元包括用于将存储在第一存储器装置中的数据信息保存到第二存储装置之一的装置，以及用于将存储在所选择的第二存储装置中的数字数据信息存储到第一存储装置中的装置。

6. 发明申请

US20070002606A1 MULTI-CONTEXT MEMORY CELL 有权
标题翻译：多媒体内存单元
公开(公告)号：US20070002606A1
公开(公告)日：2007-01-04
申请号：US11427336
申请日：2006-06-28
申请人： Thomas Niedermeier , Tim Schoenauer
发明人： Thomas Niedermeier , Tim Schoenauer
IPC分类号： G11C11/00
CPC分类号： G11C7/24 , G11C7/1006 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C14/009 , G11C2213/74
摘要： The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.
摘要翻译：多上下文存储单元包括用于存储数据信息项的第一存储器装置和多个第二存储器装置，存储在第一存储器装置中的数据信息可以被保存在每个第二存储器装置中。此外，存储单元包括用于将存储在第一存储器装置中的数据信息保存到第二存储装置之一的装置，以及用于将存储在所选择的第二存储装置中的数字数据信息存储到第一存储装置中的装置。

7. 发明授权

US07725647B2 Memory arrangement having efficient arrangement of devices 有权
标题翻译：具有设备有效布置的存储器布置
公开(公告)号：US07725647B2
公开(公告)日：2010-05-25
申请号：US11679732
申请日：2007-02-27
申请人： Paul Wallner , Tim Schoenauer , Peter Gregorius , Daniel Kehrer
发明人： Paul Wallner , Tim Schoenauer , Peter Gregorius , Daniel Kehrer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0607
摘要： A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.
摘要翻译：存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。存储器装置包括至少两个存储体。每个存储体包括至少一个存储单元。存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。至少两个数据分组处理设备被分配给不同的存储体存取设备。

8. 发明申请

US20070201296A1 MEMORY ARRANGEMENT 有权
标题翻译：内存安排
公开(公告)号：US20070201296A1
公开(公告)日：2007-08-30
申请号：US11679732
申请日：2007-02-27
申请人： Paul Wallner , Tim Schoenauer , Peter Gregorius , Daniel Kehrer
发明人： Paul Wallner , Tim Schoenauer , Peter Gregorius , Daniel Kehrer
IPC分类号： G11C8/00
CPC分类号： G06F12/0607
摘要： A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.
摘要翻译：存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。存储器装置包括至少两个存储体。每个存储体包括至少一个存储单元。存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。至少两个数据分组处理设备被分配给不同的存储体存取设备。

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