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1. 发明授权

US07465992B2 Field effect transistor with mixed-crystal-orientation channel and source/drain regions 有权
标题翻译：具有混晶取向沟道和源极/漏极区的场效应晶体管
公开(公告)号：US07465992B2
公开(公告)日：2008-12-16
申请号：US11116053
申请日：2005-04-27
申请人： Joel P. Desouza , Devendra K. Sadana , Katherine L. Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
发明人： Joel P. Desouza , Devendra K. Sadana , Katherine L. Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/7624 , H01L21/823807 , H01L21/8258 , H01L27/0605 , H01L27/0922 , H01L27/1203 , H01L29/045 , H01L29/66636 , H01L29/7833
摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.
摘要翻译：混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET）以半导体方向设置，其对于空穴迁移率是最佳的。本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。可以并入其中可并入这些新的FET的混合基板及其制造方法。

2. 发明申请

US20080224182A1 TRENCH-EDGE-DEFECT-FREE RECRYSTALLIZATION BY EDGE-ANGLE-OPTIMIZED SOLID PHASE EPITAXY: METHOD AND APPLICATIONS TO HYBRID ORIENTATION SUBSTRATES 有权
标题翻译：通过EDGE-ANGLE优化的固相相位外延梯度边缘无缺陷重构：混合定向衬底的方法和应用
公开(公告)号：US20080224182A1
公开(公告)日：2008-09-18
申请号：US12044579
申请日：2008-03-07
申请人： Katherine L. Saenger , Chun-yung Sung , Haizhou Yin
发明人： Katherine L. Saenger , Chun-yung Sung , Haizhou Yin
IPC分类号： H01L27/092
CPC分类号： H01L29/045 , C30B1/023 , C30B29/06 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203
摘要： The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane directions.
摘要翻译：本发明公开了边缘角优化固相外延形成用于形成混合取向衬底的用途，其包括当Si的沟槽分离区域重新结晶到一定方向时通常看到的没有沟槽边缘缺陷的改变取向Si器件区域在非晶化步骤之后的基础单晶Si模板。对于非晶化Si区域重结晶到（100）表面取向的情况，边缘角优化固相外延的无边缘缺陷重结晶可以在其边缘与（100）晶体的边缘对齐的直线Si器件区域中实现在平面<100>方向。

3. 发明授权

US07396407B2 Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates 有权
标题翻译：通过边缘角优化固相外延的沟槽边缘缺陷重结晶：混合取向基板的方法和应用
公开(公告)号：US07396407B2
公开(公告)日：2008-07-08
申请号：US11406123
申请日：2006-04-18
申请人： Katherine L. Saenger , Chun-yung Sung , Haizhou Yin
发明人： Katherine L. Saenger , Chun-yung Sung , Haizhou Yin
IPC分类号： C30B21/04
CPC分类号： H01L29/045 , C30B1/023 , C30B29/06 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203
摘要： The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane directions.
摘要翻译：本发明公开了边缘角优化固相外延形成用于形成混合取向衬底的用途，其包括当Si的沟槽分离区域重新结晶到一定方向时通常看到的没有沟槽边缘缺陷的改变取向Si器件区域在非晶化步骤之后的底层单晶Si模板。对于非晶化Si区域重结晶到（100）表面取向的情况，边缘角优化固相外延的无边缘缺陷重结晶可以在其边缘与（100）晶体的边缘对齐的直线Si器件区域中实现在平面<100>方向。

4. 发明授权

US07999319B2 Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates 有权
标题翻译：通过边缘角优化固相外延的沟槽边缘缺陷重结晶：混合取向基板的方法和应用
公开(公告)号：US07999319B2
公开(公告)日：2011-08-16
申请号：US12044579
申请日：2008-03-07
申请人： Katherine L. Saenger , Chun-yung Sung , Haizhou Yin
发明人： Katherine L. Saenger , Chun-yung Sung , Haizhou Yin
IPC分类号： H01L27/092
CPC分类号： H01L29/045 , C30B1/023 , C30B29/06 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203
摘要： The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane directions.
摘要翻译：本发明公开了边缘角优化固相外延形成用于形成混合取向衬底的用途，其包括当Si的沟槽分离区域重新结晶到一定方向时通常看到的没有沟槽边缘缺陷的改变取向Si器件区域在非晶化步骤之后的底层单晶Si模板。对于非晶化Si区域重结晶到（100）表面取向的情况，边缘角优化固相外延的无边缘缺陷重结晶可以在其边缘与（100）晶体的边缘对齐的直线Si器件区域中实现在平面<100>方向。

5. 发明申请

US20060244068A1 Field effect transistor with mixed-crystal-orientation channel and source/drain regions 有权
标题翻译：具有混晶取向沟道和源极/漏极区的场效应晶体管
公开(公告)号：US20060244068A1
公开(公告)日：2006-11-02
申请号：US11116053
申请日：2005-04-27
申请人： Joel Desouza , Devendra Sadana , Katherine Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
发明人： Joel Desouza , Devendra Sadana , Katherine Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
IPC分类号： H01L27/12
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/7624 , H01L21/823807 , H01L21/8258 , H01L27/0605 , H01L27/0922 , H01L27/1203 , H01L29/045 , H01L29/66636 , H01L29/7833
摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.
摘要翻译：混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET）以半导体方向设置，其对于空穴迁移率是最佳的。本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。可以并入其中可并入这些新的FET的混合基板及其制造方法。

6. 发明申请

US20070241323A1 Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates 有权
标题翻译：通过边缘角优化固相外延的沟槽边缘缺陷重结晶：混合取向基板的方法和应用
公开(公告)号：US20070241323A1
公开(公告)日：2007-10-18
申请号：US11406123
申请日：2006-04-18
申请人： Katherine Saenger , Chun-yung Sung , Haizhou Yin
发明人： Katherine Saenger , Chun-yung Sung , Haizhou Yin
IPC分类号： H01L31/00 , C30B21/04 , H01L29/04 , H01L29/10 , C30B28/14
CPC分类号： H01L29/045 , C30B1/023 , C30B29/06 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203
摘要： Edge-angle-optimized solid phase epitaxy is described as a method for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane directions. In a first aspect of the invention, twist-angle-optimized bonding and edge-angle-optimized epitaxy are applied to the fabrication of trench-edge-defect-free hybrid orientation substrates comprising (110)-oriented Si device regions in which high-performance p-channel field effect transistors (pFETs) may be formed and amorphized-and-recrystallized changed-orientation (100)-oriented Si device regions in which high-performance n-channel field effect transistors (nFETs) may be formed. In a second aspect of the invention, nFETs are fabricated in (100)-oriented Si regions in hybrid orientation substrates using edge-angle-optimized solid phase epitaxy to achieve trench-edge-defect-free amorphized-and-recrystallized source/drain regions.
摘要翻译：边缘角优化的固相外延被描述为用于形成混合定向衬底的方法，其包括当Si的沟槽分离区域被重结晶为底层单体的取向时通常看到的没有沟槽边缘缺陷的改变取向Si器件区域非晶态Si模板。对于非晶化Si区域重结晶到（100）表面取向的情况，边缘角优化固相外延的无边缘缺陷重结晶可以在其边缘与（100）晶体的边缘对齐的直线Si器件区域中实现在平面<100>方向。在本发明的第一方面中，将扭转角优化的结合和边缘角优化的外延应用于包括（110）取向的Si器件区域的无沟槽缺陷的混合取向衬底的制造，可以形成高性能p沟道场效应晶体管（pFET）和可以形成高性能n沟道场效应晶体管（nFET）的非晶化和再结晶的改变取向（100）取向（100）取向的Si器件区域。在本发明的第二方面中，使用边缘角优化的固相外延，在混合取向基板中的（100）取向的Si区域中制造nFET，以实现无沟槽边缘缺陷的非晶化和再结晶源极/漏极区域。

7. 发明授权

US08097516B2 Dual trench isolation for CMOS with hybrid orientations 有权
标题翻译：具有混合取向的CMOS的双沟槽隔离
公开(公告)号：US08097516B2
公开(公告)日：2012-01-17
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

8. 发明授权

US07943486B2 Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain 有权
标题翻译：在双轴压缩应变下，增强了<110> Si中的电子和空穴迁移率
公开(公告)号：US07943486B2
公开(公告)日：2011-05-17
申请号：US12115731
申请日：2008-05-06
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/30
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

9. 发明授权

US07314790B2 Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain 失效
公开(公告)号：US07314790B2
公开(公告)日：2008-01-01
申请号：US11612309
申请日：2006-12-18
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

10. 发明申请

US20120104511A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20120104511A1
公开(公告)日：2012-05-03
申请号：US13349203
申请日：2012-01-12
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

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