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1. 发明授权

US09018065B2 Horizontal epitaxy furnace for channel SiGe formation 有权
标题翻译：用于通道SiGe形成的水平外延炉
公开(公告)号：US09018065B2
公开(公告)日：2015-04-28
申请号：US13466234
申请日：2012-05-08
申请人： Joanna Wasyluk , Yew Tuck Chow , Stephan Kronholz , Lindarti Purwaningsih , Ines Becker
发明人： Joanna Wasyluk , Yew Tuck Chow , Stephan Kronholz , Lindarti Purwaningsih , Ines Becker
IPC分类号： H01L21/20 , H01L21/205 , H01L21/306 , H01L21/8238 , H01L21/8234 , C23C16/458 , H01L21/3065 , H01L21/02 , H01L21/67 , C23C16/455
CPC分类号： H01L21/823807 , C23C16/45578 , C23C16/4587 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823412 , H01L21/823878
摘要： A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.
摘要翻译：提供一种方法和装置，用于在水平取向的处理炉内的凹陷区域内凹陷PFET的沟道区和外延生长沟道SiGe。实施例包括在晶片的前侧形成n沟道区域和p沟道区域以及至少一个附加晶片，n沟道区域和p沟道区域分别对应于用于形成NFET和PFET的位置; 将晶片放置在具有顶表面和底表面的水平取向的炉中，其中晶片在顶表面和底表面之间垂直取向; 使炉内的晶片的p沟道区域凹陷; 并且在炉内凹陷的p沟道区中外延生长cSiGe，而没有孔缺陷。

2. 发明申请

US20130302973A1 HORIZONTAL EPITAXY FURNACE FOR CHANNEL SIGE FORMATION 有权
标题翻译：水平信号形成的水平外露炉
公开(公告)号：US20130302973A1
公开(公告)日：2013-11-14
申请号：US13466234
申请日：2012-05-08
申请人： Joanna Wasyluk , Yew Tuck Chow , Stephan Kronholz , Lindarti Purwaningsih , Ines Becker
发明人： Joanna Wasyluk , Yew Tuck Chow , Stephan Kronholz , Lindarti Purwaningsih , Ines Becker
IPC分类号： H01L21/205 , H01L21/306
CPC分类号： H01L21/823807 , C23C16/45578 , C23C16/4587 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823412 , H01L21/823878
摘要： A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.
摘要翻译：提供一种方法和装置，用于在水平取向的处理炉内的凹陷区域内凹陷PFET的沟道区和外延生长沟道SiGe。实施例包括在晶片的前侧形成n沟道区域和p沟道区域以及至少一个附加晶片，n沟道区域和p沟道区域分别对应于用于形成NFET和PFET的位置; 将晶片放置在具有顶表面和底表面的水平取向的炉中，其中晶片在顶表面和底表面之间垂直取向; 使炉内的晶片的p沟道区域凹陷; 并且在炉内凹陷的p沟道区中外延生长cSiGe，而没有孔缺陷。

3. 发明授权

US08658543B2 Methods for pFET fabrication using APM solutions 有权
标题翻译：使用APM解决方案的pFET制造方法
公开(公告)号：US08658543B2
公开(公告)日：2014-02-25
申请号：US13368055
申请日：2012-02-07
申请人： Joanna Wasyluk , Stephan Kronholz , Yew-Tuck Chow , Richard J. Carter , Berthold Reimer , Kai Tern Sih
发明人： Joanna Wasyluk , Stephan Kronholz , Yew-Tuck Chow , Richard J. Carter , Berthold Reimer , Kai Tern Sih
IPC分类号： H01L21/302
CPC分类号： H01L21/30604 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.
摘要翻译：公开了一种用于制造集成电路的方法，其包括根据实施例提供包括p型场效应晶体管（pFET）的集成电路，使用氨 - 过氧化氢 - 水（pFET）凹陷pFET的表面区域 APM）溶液以形成凹陷的pFET表面区域，以及在凹陷的pFET表面区域上沉积硅基材料通道。

4. 发明申请

US20130203244A1 METHODS FOR PFET FABRICATION USING APM SOLUTIONS 有权
标题翻译：使用APM解决方案的PFET制造方法
公开(公告)号：US20130203244A1
公开(公告)日：2013-08-08
申请号：US13368055
申请日：2012-02-07
申请人： Joanna Wasyluk , Stephan Kronholz , Yew-Tuck Chow , Richard J. Carter , Berthold Reimer , Kai Tern Sih
发明人： Joanna Wasyluk , Stephan Kronholz , Yew-Tuck Chow , Richard J. Carter , Berthold Reimer , Kai Tern Sih
IPC分类号： H01L21/20
CPC分类号： H01L21/30604 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.
摘要翻译：公开了一种用于制造集成电路的方法，其包括根据实施例提供包括p型场效应晶体管（pFET）的集成电路，使用氨 - 过氧化氢 - 水（pFET）凹陷pFET的表面区域 APM）溶液以形成凹陷的pFET表面区域，以及在凹陷的pFET表面区域上沉积硅基材料通道。

5. 发明申请

US20130299874A1 TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE 审中-公开
标题翻译：用于CMOS器件的正极通道区域中的硅锗的TMAH接收
公开(公告)号：US20130299874A1
公开(公告)日：2013-11-14
申请号：US13468777
申请日：2012-05-10
申请人： Joanna Wasyluk , Berthold Reimer , Carsten Reichel , Jamie Schaeffer , Yew Tuck Chow , Stephan Kronholz , Andreas Ott
发明人： Joanna Wasyluk , Berthold Reimer , Carsten Reichel , Jamie Schaeffer , Yew Tuck Chow , Stephan Kronholz , Andreas Ott
IPC分类号： H01L27/092 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/02057 , H01L21/30608 , H01L21/823878
摘要： CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region.
摘要翻译：通过在正通道中形成用于沉积SiGe的凹槽来增强CMOS器件。实施例包括在用于CMOS器件的硅衬底中提供正沟道区和负沟道区，其间具有STI区; 从正通道区域上方去除天然氧化物以暴露硅衬底; 在与STI区域相邻的正沟道区域中的硅衬底中形成凹部; 以及将SiGe沉积在正沟道区中的凹槽中，其中SiGe的上表面与负沟道区的上表面基本一致。

6. 发明授权

US08703620B2 Methods for PFET fabrication using APM solutions 有权
标题翻译：使用APM解决方案的PFET制造方法
公开(公告)号：US08703620B2
公开(公告)日：2014-04-22
申请号：US13564071
申请日：2012-08-01
申请人： Joanna Wasyluk , Stephan Kronholz , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
发明人： Joanna Wasyluk , Stephan Kronholz , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L21/30604 , H01L21/30608 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
摘要翻译：一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。第一部分和第二部分通过浅沟槽隔离特征电隔离。该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

7. 发明申请

US20140051227A1 METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS 有权
标题翻译：通过实施干式化学除去工艺形成半导体器件的隔离结构的方法
公开(公告)号：US20140051227A1
公开(公告)日：2014-02-20
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

8. 发明授权

US08716102B2 Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process 有权
标题翻译：通过干式化学去除方法形成半导体器件隔离结构的方法
公开(公告)号：US08716102B2
公开(公告)日：2014-05-06
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L27/092
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

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