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1. 发明授权

US08606987B2 Data writing method for flash memory and controller using the same 有权
标题翻译： Flash存储器的数据写入方法及使用其的控制器
公开(公告)号：US08606987B2
公开(公告)日：2013-12-10
申请号：US12052348
申请日：2008-03-20
申请人： Jiunn-Yeong Yang , Jui-Hsien Chang , Chien-Hua Chu , Jian-Yo Su , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Jui-Hsien Chang , Chien-Hua Chu , Jian-Yo Su , Chih-Kang Yeh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the size of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the size of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the size of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the size of the writing unit into the temporary area and then writing the sub-data not having the size of the writing unit with subsequent data into the substitute block.
摘要翻译：提供了一种用于闪速存储器的数据写入方法。数据写入方法包括：按照写入单元的大小将新数据划分为至少一个子数据; 从闪存中选择多个备用块中的一个作为用于替换数据块的替代块，其中新数据将被写入数据块; 将具有写入单元的大小的子数据顺序地写入写入单元中的替代块; 并将不具有写入单元大小的子数据存储在临时区域中。通过将不具有写入单元的大小的子数据临时存储到临时区域中，然后将不具有后续数据的具有写入单元的大小的子数据写入替代物，可以提高闪速存储器的写入效率块。

2. 发明申请

US20090150597A1 DATA WRITING METHOD FOR FLASH MEMORY AND CONTROLLER USING THE SAME 有权
标题翻译：闪存存储器的数据写入方法和使用该存储器的控制器
公开(公告)号：US20090150597A1
公开(公告)日：2009-06-11
申请号：US12052348
申请日：2008-03-20
申请人： Jiunn-Yeong Yang , Jui-Hsien Chang , Chien-Hua Chu , Jian-Yo Su , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Jui-Hsien Chang , Chien-Hua Chu , Jian-Yo Su , Chih-Kang Yeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block.
摘要翻译：提供了一种用于闪速存储器的数据写入方法。数据写入方法包括：将新数据分割为一个写入单元长度的一个子数据; 从闪存中选择多个备用块中的一个作为用于替换数据块的替代块，其中新数据将被写入数据块; 将具有写入单元的长度的子数据顺序地写入写入单元中的替换块; 以及将不具有写入单元的长度的子数据存储在临时区域中。通过将不具有写入单元的长度的子数据临时存储到临时区域中，然后将不具有写入单元的长度的子数据与后续数据写入替代物，可以提高闪速存储器的写入效率块。

3. 发明申请

US20100042774A1 BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME 审中-公开
标题翻译：闪存存储器的块管理方法，存储系统和使用该存储器的控制器
公开(公告)号：US20100042774A1
公开(公告)日：2010-02-18
申请号：US12265429
申请日：2008-11-05
申请人： Jiunn-Yeong Yang , Chien-Hua Chu , Chih-Kang Yeh , Kuang-Tung Fang , Jui-Hsien Chang
发明人： Jiunn-Yeong Yang , Chien-Hua Chu , Chih-Kang Yeh , Kuang-Tung Fang , Jui-Hsien Chang
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： A block management method for a flash memory chip having multiple planes is provided, wherein each plane has a plurality of physical blocks. The method includes disposing a plurality of physical units, wherein each physical unit includes a physical block of each plane, and the physical blocks in the physical unit have a simultaneously-operable relationship. The method also includes writing data in a single plane access mode when a host system does not update all the physical blocks in an updated the physical unit. The method further includes writing the data in a multi-planes access mode when the host system updates all the physical blocks in the updated physical unit, wherein the physical blocks for writing the data have the simultaneously-operable relationship.
摘要翻译：提供了一种具有多个平面的闪存芯片的块管理方法，其中每个平面具有多个物理块。该方法包括布置多个物理单元，其中每个物理单元包括每个平面的物理块，物理单元中的物理块具有同时可操作的关系。该方法还包括当主机系统不更新更新的物理单元中的所有物理块时，以单平面访问模式写入数据。该方法还包括当主机系统更新更新的物理单元中的所有物理块时，以多平面访问模式写入数据，其中用于写入数据的物理块具有同时可操作的关系。

4. 发明申请

US20090300271A1 STORAGE SYSTEM HAVING MULTIPLE NON-VOLATILE MEMORIES, AND CONTROLLER AND ACCESS METHOD THEREOF 有权
标题翻译：具有多个非易失性存储器的存储系统及其控制器及其访问方法
公开(公告)号：US20090300271A1
公开(公告)日：2009-12-03
申请号：US12197468
申请日：2008-08-25
申请人： Jiunn-Yeong Yang , Chien-Hua Chu , Kuo-Yi Cheng , Li-Chun Liang , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Chien-Hua Chu , Kuo-Yi Cheng , Li-Chun Liang , Chih-Kang Yeh
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/06 , G06F2212/2022
摘要： A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.
摘要翻译：提供了包括传输接口，存储器模块和控制器的非易失性存储器存储系统。存储器模块包括第一和第二非易失性存储器芯片。可以通过经由芯片使能引脚从控制器接收芯片使能信号来同时启用第一和第二非易失性存储器芯片。当控制器执行多通道访问时，在使能具有芯片使能信号的第一非易失性存储器芯片和第二非易失性存储器芯片之后，控制器向第一和第二非易失性存储器芯片提供访问指令。当控制器执行单通道访问时，控制器将访问信号提供给第一和第二非易失性存储器芯片中的一个，并且在启用第一非易失性存储器芯片之后提供另一个非访问指令，具有芯片使能信号的第二非易失性存储器芯片。

5. 发明授权

US07975096B2 Storage system having multiple non-volatile memories, and controller and access method thereof 有权
标题翻译：具有多个非易失性存储器的存储系统及其控制器及其访问方法
公开(公告)号：US07975096B2
公开(公告)日：2011-07-05
申请号：US12197468
申请日：2008-08-25
申请人： Jiunn-Yeong Yang , Chien-Hua Chu , Kuo-Yi Cheng , Li-Chun Liang , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Chien-Hua Chu , Kuo-Yi Cheng , Li-Chun Liang , Chih-Kang Yeh
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F2212/2022
摘要： A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.
摘要翻译：提供了包括传输接口，存储器模块和控制器的非易失性存储器存储系统。存储器模块包括第一和第二非易失性存储器芯片。可以通过经由芯片使能引脚从控制器接收芯片使能信号来同时启用第一和第二非易失性存储器芯片。当控制器执行多通道访问时，在使能具有芯片使能信号的第一非易失性存储器芯片和第二非易失性存储器芯片之后，控制器向第一和第二非易失性存储器芯片提供访问指令。当控制器执行单通道访问时，控制器将访问信号提供给第一和第二非易失性存储器芯片中的一个，并且在启用第一非易失性存储器芯片之后，向另一个提供非访问指令，具有芯片使能信号的第二非易失性存储器芯片。

6. 发明授权

US08131911B2 Data writing method, and flash storage system and controller using the same 有权
标题翻译：数据写入方式，以及Flash存储系统和控制器的使用方法
公开(公告)号：US08131911B2
公开(公告)日：2012-03-06
申请号：US12147969
申请日：2008-06-27
申请人： Jiunn-Yeong Yang , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Chih-Kang Yeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1024 , G06F2212/7202
摘要： A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system.
摘要翻译：提供数据写入方法，闪存存储系统和使用它们的控制器。该方法包括将闪存的物理块分组成数据区，备用区和特殊区的物理块。该方法还包括当更新数据是单个访问单元时将更新数据写入特殊区域的相应物理块。该方法可以包括在每个数据写入命令期间将映射到更新数据所属的逻辑块的物理块中的一部分有效数据移动到备用区的物理块中。因此，可以减少每个数据写入命令的响应时间，从而防止由闪存存储系统配置的具有大擦除单元的闪速存储器引起的超时问题。

7. 发明申请

US20090265505A1 DATA WRITING METHOD, AND FLASH STORAGE SYSTEM AND CONTROLLER USING THE SAME 有权
标题翻译：数据写入方法和闪存存储系统以及使用它的控制器
公开(公告)号：US20090265505A1
公开(公告)日：2009-10-22
申请号：US12147969
申请日：2008-06-27
申请人： Jiunn-Yeong Yang , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Chih-Kang Yeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1024 , G06F2212/7202
摘要： A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system.
摘要翻译：提供数据写入方法，闪存存储系统和使用它们的控制器。该方法包括将闪存的物理块分组成数据区，备用区和特殊区的物理块。该方法还包括当更新数据是单个访问单元时将更新数据写入特殊区域的相应物理块。该方法可以包括在每个数据写入命令期间将映射到更新数据所属的逻辑块的物理块中的一部分有效数据移动到备用区的物理块中。因此，可以减少每个数据写入命令的响应时间，从而防止由闪存存储系统配置的具有大擦除单元的闪速存储器引起的超时问题。

8. 发明授权

US08607123B2 Control circuit capable of identifying error data in flash memory and storage system and method thereof 有权
标题翻译：能够识别闪存和存储系统中的错误数据的控制电路及其方法
公开(公告)号：US08607123B2
公开(公告)日：2013-12-10
申请号：US12542130
申请日：2009-08-17
申请人： Jiunn-Yeong Yang , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Chih-Kang Yeh
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04
摘要： A flash memory control circuit including a microprocessor unit, a first interface unit for connecting a flash memory, a second interface unit for connecting a computer host, an error correcting unit, a memory management unit, and a marking unit is provided. The memory management unit divides each page in the flash memory into a plurality of data bit areas, and a plurality of redundancy bit areas and a plurality of error correcting bit areas corresponding to the data bit areas, wherein each of the data bit areas has a plurality of sectors for respectively storing a sector data. The marking unit stores a data accuracy mark corresponding to each sector data in the corresponding redundancy bit area to record the status of the sector data. Thereby, the flash memory controller can effectively identify error data in the flash memory by using the error correcting codes and the data accuracy marks.
摘要翻译：提供一种闪存控制电路，包括微处理器单元，用于连接闪存的第一接口单元，用于连接计算机主机的第二接口单元，纠错单元，存储器管理单元和标记单元。存储器管理单元将闪速存储器中的每一页划分成多个数据位区域，以及与数据位区域相对应的多个冗余位区域和多个纠错位区域，其中每个数据位区域具有多个扇区用于分别存储扇区数据。标记单元将对应于每个扇区数据的数据精度标记存储在相应的冗余位区域中，以记录扇区数据的状态。由此，闪存控制器可以通过使用纠错码和数据精度标记来有效地识别闪速存储器中的错误数据。

9. 发明授权

US08776232B2 Controller capable of preventing spread of computer viruses and storage system and method thereof 有权
标题翻译：能够防止计算机病毒和存储系统扩散的控制器及其方法
公开(公告)号：US08776232B2
公开(公告)日：2014-07-08
申请号：US12504947
申请日：2009-07-17
申请人： Jiunn-Yeong Yang , Chien-Fu Lee , Ming-Chou Wu
发明人： Jiunn-Yeong Yang , Chien-Fu Lee , Ming-Chou Wu
IPC分类号： G06F12/14 , G06F21/56 , G06F21/14 , G06F21/80 , G06F21/85 , G06F21/60 , H04L29/06
CPC分类号： G06F21/566 , G06F21/14 , G06F21/56 , G06F21/606 , G06F21/80 , G06F21/85 , H04L63/145
摘要： A controller capable of preventing spread of computer viruses is provided. The controller includes a microprocessor unit, and a first interface unit, a second interface unit, a comparing unit and a filter unit which are coupled to the microprocessor unit. The first interface unit is coupled to a storage medium, and the second interface unit is coupled to a computer host. The comparing unit determines whether data read form the storage medium by the computer host is an automatic executing file. And, the filter unit replaces the read data with a predetermined data and transmit the predetermined data to the computer host when the read data is the automatic executing file. Accordingly, the controller is capable of preventing the spread of the computer viruses designed in an automatic executing file.
摘要翻译：提供了能够防止计算机病毒扩散的控制器。控制器包括微处理器单元，以及耦合到微处理器单元的第一接口单元，第二接口单元，比较单元和滤波器单元。第一接口单元耦合到存储介质，并且第二接口单元耦合到计算机主机。比较单元确定由计算机主机从存储介质读取的数据是否是自动执行文件。并且，当读取的数据是自动执行文件时，滤波器单元用预定数据替换读取的数据并将预定数据发送到计算机主机。因此，控制器能够防止在自动执行文件中设计的计算机病毒的扩展。

10. 发明申请

US20100058073A1 STORAGE SYSTEM, CONTROLLER, AND DATA PROTECTION METHOD THEREOF 审中-公开
标题翻译：存储系统，控制器和数据保护方法
公开(公告)号：US20100058073A1
公开(公告)日：2010-03-04
申请号：US12345444
申请日：2008-12-29
申请人： Hon-Wai Ng , Ching-Wen Chang , Jiunn-Yeong Yang , Chee-Kong Awyong
发明人： Hon-Wai Ng , Ching-Wen Chang , Jiunn-Yeong Yang , Chee-Kong Awyong
IPC分类号： G06F12/14 , H04L9/32
CPC分类号： H04L9/3226 , H04L9/0897 , H04L9/3236
摘要： A storage system including a storage unit, a connector, and a controller is provided. A personal identification number (PIN) message digest and a cipher text are stored in the storage unit. When the storage system is connected to a host system through the connector, the controller requests a password from the host system and generates a message digest through a one-way hash function according to the password. After that, the controller determinates whether the message digest matches the PIN message digest. If the message digest matches the PIN message digest, the controller decrypts the cipher text in the storage unit through a first encryption/decryption function according to the password to obtain an encryption/decryption key. Eventually, the controller encrypts and decrypts user data through a second encryption/decryption function according to the encryption/decryption key. Thereby, the user data stored in the storage system can be effectively protected.
摘要翻译：提供了包括存储单元，连接器和控制器的存储系统。个人识别码（PIN）消息摘要和密文存储在存储单元中。当存储系统通过连接器连接到主机系统时，控制器从主机系统请求密码，并根据密码通过单向散列函数生成消息摘要。之后，控制器确定消息摘要是否与PIN消息摘要相匹配。如果消息摘要符合PIN消息摘要，则控制器通过根据密码的第一加密/解密功能来解密存储单元中的密文，以获得加密/解密密钥。最终，控制器根据加密/解密密钥通过第二加密/解密功能对用户数据进行加密和解密。从而可以有效地保护存储在存储系统中的用户数据。

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