专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08592318B2 Pitch reduction using oxide spacer 有权
标题翻译：使用氧化物间隔物进行减径
公开(公告)号：US08592318B2
公开(公告)日：2013-11-26
申请号：US12742073
申请日：2008-11-07
申请人： Jisoo Kim , Conan Chiang , Jun Shinagawa , S. M. Reza Sadjadi
发明人： Jisoo Kim , Conan Chiang , Jun Shinagawa , S. M. Reza Sadjadi
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31144 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/0337 , H01L21/0338 , H01L21/31612 , H01L21/31654 , H01L21/32139
摘要： A method for etching an etch layer disposed over a substrate and below an antireflective coating (ARC) layer and a patterned organic mask with mask features is provided. The substrate is placed in a process chamber. The ARC layer is opened. An oxide spacer deposition layer is formed. The oxide spacer deposition layer on the organic mask is partially removed, where at least the top portion of the oxide spacer deposition layer is removed. The organic mask and the ARC layer are removed by etching. The etch layer is etched through the sidewalls of the oxide spacer deposition layer. The substrate is removed from the process chamber.
摘要翻译：提供了一种用于蚀刻设置在基板上方并且在抗反射涂层（ARC）层下方的蚀刻层和具有掩模特征的图案化有机掩模的方法。将基板放置在处理室中。 ARC层打开。形成氧化物间隔物沉积层。部分去除有机掩模上的氧化物间隔物沉积层，其中氧化物间隔物沉积层的至少顶部被去除。通过蚀刻除去有机掩模和ARC层。通过氧化物隔离层沉积层的侧壁蚀刻蚀刻层。将衬底从处理室中取出。

2. 发明授权

US08357434B1 Apparatus for the deposition of a conformal film on a substrate and methods therefor 有权
标题翻译：用于在基底上沉积保形膜的装置及其方法
公开(公告)号：US08357434B1
公开(公告)日：2013-01-22
申请号：US11304223
申请日：2005-12-13
申请人： Dae-han Choi , Jisoo Kim , Eric Hudson , Sangheon Lee , Conan Chiang , S. M. Reza Sadjadi
发明人： Dae-han Choi , Jisoo Kim , Eric Hudson , Sangheon Lee , Conan Chiang , S. M. Reza Sadjadi
IPC分类号： H05H1/24
CPC分类号： H01L21/0338 , H01J37/32082 , H01J37/32449 , H01J37/32724 , H01J37/32834
摘要： A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film.
摘要翻译：公开了一种在等离子体处理系统的等离子体处理室中的基板上沉积保形膜的方法，该基板设置在卡盘上，该卡盘与冷却装置连接。该方法包括在第一压力下将第一气体混合物流入等离子体处理室，其中第一气体混合物至少包括碳，并且其中第一气体混合物具有冷凝温度。该方法还包括使用冷却装置将夹盘冷却至冷凝温度以下，从而允许至少一些第一气体混合物在基板的表面上冷凝。该方法还包括从处理室排出第一气体混合物; 将第二气体混合物流入等离子体处理室，第二气体混合物的组成与第一气体混合物不同; 并冲击等离子体以形成保形膜。

3. 发明申请

US20120052683A1 PITCH REDUCTION USING OXIDE SPACER 有权
标题翻译：使用氧化物间距减少PITCH
公开(公告)号：US20120052683A1
公开(公告)日：2012-03-01
申请号：US12742073
申请日：2008-11-07
申请人： Jisoo Kim , Conan Chiang , Jun Shinagawa , S.M. Reza Sadjadi
发明人： Jisoo Kim , Conan Chiang , Jun Shinagawa , S.M. Reza Sadjadi
IPC分类号： H01L21/302 , B23K10/00
CPC分类号： H01L21/31144 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/0337 , H01L21/0338 , H01L21/31612 , H01L21/31654 , H01L21/32139
摘要： A method for etching an etch layer disposed over a substrate and below an antireflective coating (ARC) layer and a patterned organic mask with mask features is provided. The substrate is placed in a process chamber. The ARC layer is opened. An oxide spacer deposition layer is formed. The oxide spacer deposition layer on the organic mask is partially removed, where at least the top portion of the oxide spacer deposition layer is removed. The organic mask and the ARC layer are removed by etching. The etch layer is etched through the sidewalls of the oxide spacer deposition layer. The substrate is removed from the process chamber.
摘要翻译：提供了一种用于蚀刻设置在基板上方并且在抗反射涂层（ARC）层下方的蚀刻层和具有掩模特征的图案化有机掩模的方法。将基板放置在处理室中。 ARC层打开。形成氧化物间隔物沉积层。部分去除有机掩模上的氧化物间隔物沉积层，其中氧化物间隔物沉积层的至少顶部被去除。通过蚀刻去除有机掩模和ARC层。通过氧化物隔离层沉积层的侧壁蚀刻蚀刻层。将衬底从处理室中取出。

4. 发明授权

US07476610B2 Removable spacer 有权
标题翻译：可拆卸垫片
公开(公告)号：US07476610B2
公开(公告)日：2009-01-13
申请号：US11598242
申请日：2006-11-10
申请人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
发明人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
IPC分类号： H01L21/44
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.
摘要翻译：提供了一种用于形成半导体器件的方法。栅极堆叠形成在衬底的表面上。提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相聚合物在基材的表面上并且形成沉积材料的轮廓。使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。去除聚合物间隔物。

5. 发明申请

US20080111166A1 Removable spacer 有权
标题翻译：可拆卸垫片
公开(公告)号：US20080111166A1
公开(公告)日：2008-05-15
申请号：US11598242
申请日：2006-11-10
申请人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
发明人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.
摘要翻译：提供了一种用于形成半导体器件的方法。栅极堆叠形成在衬底的表面上。提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相聚合物在基材的表面上并且形成沉积材料的轮廓。使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。去除聚合物间隔物。

6. 发明申请

US20070181530A1 Reducing line edge roughness 审中-公开
标题翻译：减少线边缘粗糙度
公开(公告)号：US20070181530A1
公开(公告)日：2007-08-09
申请号：US11350488
申请日：2006-02-08
申请人： Zhi-Song Huang , S.M. Sadjadi , Lumin Li , Conan Chiang
发明人： Zhi-Song Huang , S.M. Sadjadi , Lumin Li , Conan Chiang
IPC分类号： C23F1/00 , H01L21/461 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： A method of forming features in an etch layer disposed below a mask with features is provided. The mask is conditioned. The conditioning, comprising providing a conditioning gas consisting essentially of at least one noble gas, forming a plasma from the conditioning gas, and exposing the mask to the plasma from the conditioning gas. The features of the mask are shrunk. Features are etched into the etch layer through the shrunk features of the mask.
摘要翻译：提供了一种在具有特征的掩模下方设置的蚀刻层中形成特征的方法。面具是有条件的。该调理装置包括提供基本上由至少一种惰性气体组成的调节气体，从调节气体形成等离子体，以及将掩模从调节气体暴露于等离子体。面具的特征缩小。通过掩模的收缩特征将特征蚀刻到蚀刻层中。

7. 发明授权

US06617257B2 Method of plasma etching organic antireflective coating 有权
标题翻译：等离子体蚀刻有机抗反射涂层的方法
公开(公告)号：US06617257B2
公开(公告)日：2003-09-09
申请号：US09820737
申请日：2001-03-30
申请人： Tuqiang Ni , Weinan Jiang , Conan Chiang , Frank Y. Lin , Chris Lee , Dai N. Lee
发明人： Tuqiang Ni , Weinan Jiang , Conan Chiang , Frank Y. Lin , Chris Lee , Dai N. Lee
IPC分类号： H01L21302
CPC分类号： B81C1/00595 , H01L21/31138 , H01L21/31144 , H01L21/67069 , H01L21/76807 , H01L21/7681 , H01L21/76838
摘要： A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.
摘要翻译：半导体制造方法，其中用无氧的含硫气体蚀刻有机抗反射涂层，其提供相对于下层的选择性和/或最小化上覆光致抗蚀剂的横向蚀刻速率以维持由光致抗蚀剂限定的临界尺寸。蚀刻剂气体可以包括SO 2和诸如Ar或He的载气和任选的其它气体例如HBr的添加物。该方法对于在形成结构如镶嵌结构中蚀刻0.25微米和较小的接触或通孔开口是有用的。

8. 发明授权

US07690966B1 Method and apparatus for detecting planarization of metal films prior to clearing 有权
标题翻译：清除前检测金属膜平面化的方法和装置
公开(公告)号：US07690966B1
公开(公告)日：2010-04-06
申请号：US12177067
申请日：2008-07-21
申请人： Ramesh Gopalan , Sridharan Srivatsan , Katgenhalli Y. Ramanujam , Tom Ni , Conan Chiang
发明人： Ramesh Gopalan , Sridharan Srivatsan , Katgenhalli Y. Ramanujam , Tom Ni , Conan Chiang
IPC分类号： B24B49/00
CPC分类号： H01L21/7684 , H01L22/20
摘要： A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.
摘要翻译：提供了一种用于平面化半导体衬底的方法。该方法通过跟踪对应于设置在半导体衬底上的导电膜的厚度的信号来启动。然后，从表示跟踪信号的数据计算二阶导数。接下来，基于二次导数的变化来识别平面化的开始。还提供了被配置为识别CMP操作的阶段之间的转变的CMP系统。

9. 发明授权

US07413988B1 Method and apparatus for detecting planarization of metal films prior to clearing 失效
标题翻译：清除前检测金属膜平面化的方法和装置
公开(公告)号：US07413988B1
公开(公告)日：2008-08-19
申请号：US10607606
申请日：2003-06-27
申请人： Ramesh Gopalan , Sridharan Srivatsan , Katgenhalli Y. Ramanujam , Tom Ni , Conan Chiang
发明人： Ramesh Gopalan , Sridharan Srivatsan , Katgenhalli Y. Ramanujam , Tom Ni , Conan Chiang
IPC分类号： H01L21/302
CPC分类号： H01L21/7684 , H01L22/20
摘要： A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.
摘要翻译：提供了一种用于平面化半导体衬底的方法。该方法通过跟踪对应于设置在半导体衬底上的导电膜的厚度的信号来启动。然后，从表示跟踪信号的数据计算二阶导数。接下来，基于二次导数的变化来识别平面化的开始。还提供了被配置为识别CMP操作的阶段之间的转变的CMP系统。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式