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    • 4. 发明授权
    • Systems and methods for equalizer optimization in a storage access retry
    • 存储访问重试中均衡器优化的系统和方法
    • US07948699B2
    • 2011-05-24
    • US12348236
    • 2009-01-02
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • G11B5/09
    • G11B20/10009G11B20/10046G11B20/10055G11B20/10481G11B20/18G11B2020/183G11B2220/2516
    • Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
    • 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。
    • 6. 发明申请
    • Systems and Methods for Equalizer Optimization in a Storage Access Retry
    • 存储访问重试中均衡器优化的系统和方法
    • US20100172046A1
    • 2010-07-08
    • US12348236
    • 2009-01-02
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • G11B20/10
    • G11B20/10009G11B20/10046G11B20/10055G11B20/10481G11B20/18G11B2020/183G11B2220/2516
    • Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
    • 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。
    • 9. 发明授权
    • Branch-metric calibration using varying bandwidth values
    • 使用不同带宽值的分支校准校准
    • US08312359B2
    • 2012-11-13
    • US12562200
    • 2009-09-18
    • Jingfeng LiuHongwei SongLingyan Sun
    • Jingfeng LiuHongwei SongLingyan Sun
    • H03M13/03G06F11/00
    • H03M13/1102H03M13/296H03M13/3961H03M13/41H03M13/6343
    • In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.
    • 在一个实施例中,信号处理接收机具有分支量测校准(BMC)单元,其接收(i)来自信道检测器的四个硬判决位的集合,以及(ii)噪声估计。 BMC单元具有两个或多个更新块(例如抽头重量更新和/或偏置补偿块),其生成由信道检测器的分支度量单元使用的更新参数以改善信道检测。 两个或多个更新块基于(i)四个硬判决位的集合,(ii)噪声估计和(iii)带宽值)来生成更新的参数。 选择两个或多个更新块中的至少两个的带宽值使得它们彼此不同。 选择不同的带宽值可以通过选择彼此相同的带宽值来实现的比特错误率降低接收机的比特误码率。