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1. 发明申请

US20130050005A1 Read Channel With Oversampled Analog To Digital Conversion And Parallel Data Detectors 审中-公开
标题翻译：读取通道与过采样模数转换和并行数据检测器
公开(公告)号：US20130050005A1
公开(公告)日：2013-02-28
申请号：US13215815
申请日：2011-08-23
申请人： Jingfeng Liu , Nayak Ratnakar Aravind , Hongwei Song , Haotian Zhang
发明人： Jingfeng Liu , Nayak Ratnakar Aravind , Hongwei Song , Haotian Zhang
IPC分类号： H03M1/12
CPC分类号： H04L25/067 , G11B20/10037 , H03H17/04 , H03H17/06 , H03H21/0012 , H03H2017/0247 , H03H2017/0297
摘要： Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors.
摘要翻译：提供了用于使用选择性过采样模数转换处理读通道中的信号的方法和装置。所公开的选择性过采样模数转换通过将均衡和/或滤波处理的至少一部分转移到数字域来简化了模拟设计。将过采样的模数转换应用于模拟输入信号，以产生给定位间隔的多个数字采样。将给定位间隔的多个数字样本应用于相应的多个数据检测器以获得检测到的输出。给定比特间隔的多个数字样本可以具有相对于彼此的相位偏移。检测的输出可以例如通过对多个数据检测器的输出求和或者通过聚合多个数据检测器的加权输出来获得。

2. 发明授权

US08610608B2 Systems and methods for reduced latency loop correction 有权
标题翻译：用于减少等待时间循环校正的系统和方法
公开(公告)号：US08610608B2
公开(公告)日：2013-12-17
申请号：US13415430
申请日：2012-03-08
申请人： Nayak Ratnakar Aravind , Scott M. Dziak , Haitao Xia
发明人： Nayak Ratnakar Aravind , Scott M. Dziak , Haitao Xia
IPC分类号： H03M1/06
CPC分类号： H03J7/04
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，讨论了包括数据检测器电路，低延迟检测电路和误差计算电路的数据处理电路。数据检测器电路可操作以对从数据输入导出的第一信号执行数据检测处理，以产生检测到的输出，并提供循环误差作为检测到的输出与第一信号之间的差。低延迟检测电路可操作以处理从数据输入得到的第二信号以产生快速检测器输出，并且将产生的误差提供为快速检测器输出和第二信号之间的差。误差计算电路可操作以至少部分地基于所产生的误差和环路误差来计算误差值。

3. 发明申请

US20130198421A1 Systems and Methods for Digital MRA Compensation 有权
标题翻译：数字MRA补偿系统与方法
公开(公告)号：US20130198421A1
公开(公告)日：2013-08-01
申请号：US13362466
申请日：2012-01-31
申请人： Nayak Ratnakar Aravind , Yu Liao , Haitao Xia
发明人： Nayak Ratnakar Aravind , Yu Liao , Haitao Xia
IPC分类号： G06F13/12
CPC分类号： H03M1/12 , G06F13/385
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，讨论了包括：模数转换器电路和磁阻调节电路的数据处理系统。模数转换器电路可操作以将输入信号转换成对应的数字采样。磁阻调节电路可操作以由于由磁阻头感测而产生校正输出，从而减少数字采样中的信号不对称性。

4. 发明授权

US08467141B2 Read channel with oversampled analog to digital conversion 有权
标题翻译：通过过采样模数转换读取通道
公开(公告)号：US08467141B2
公开(公告)日：2013-06-18
申请号：US13215803
申请日：2011-08-23
申请人： James A. Bailey , Nayak Ratnakar Aravind , Erich F. Haratsch
发明人： James A. Bailey , Nayak Ratnakar Aravind , Erich F. Haratsch
IPC分类号： G11B5/09 , G11B27/36
CPC分类号： G11B20/10009
摘要： Methods and apparatus are provided for processing a signal in a read channel using an oversampled analog to digital conversion. An oversampled analog to digital conversion is performed on an analog input signal to generate a plurality of digital samples corresponding to the analog input signal for a given bit interval. A data detection algorithm can then be applied on one or more of the digital samples to obtain a detected output. The oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain.
摘要翻译：提供了用于使用过采样的模数转换处理读通道中的信号的方法和装置。在模拟输入信号上执行过采样的模数转换，以在给定的位间隔上产生对应于模拟输入信号的多个数字采样。然后可以将数据检测算法应用于一个或多个数字样本以获得检测到的输出。过采样模数转换通过将至少一部分均衡和/或滤波处理转移到数字域来简化了模拟设计。

5. 发明授权

US08462455B2 Systems and methods for improved servo data operation 有权
标题翻译：改进伺服数据操作的系统和方法
公开(公告)号：US08462455B2
公开(公告)日：2013-06-11
申请号：US12992940
申请日：2008-09-29
申请人： Nayak Ratnakar Aravind
发明人： Nayak Ratnakar Aravind
IPC分类号： G11B5/09 , G11B5/596
CPC分类号： G11B20/18 , G11B5/584 , G11B5/59688
摘要： Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data.
摘要翻译：本发明的各种实施例提供了用于有效地确定头部相对于存储介质的位置误差的系统，方法和媒体格式。在一种情况下，公开了一种包括具有一系列数据的存储介质的系统。一系列数据包括第一定义标记和位于距离第一定义标记的距离的第二定义标记和位置位置数据。所述系统还包括第一检测器电路，其可操作以检测第一定义标记并建立第一定义标记的位置，以及第二检测器电路，其可操作以检测第二定义标记并建立第二定义标记的位置定义标记。该系统还包括误差计算电路和内插电路。误差计算电路可操作以至少部分地基于第一定义标记的位置和第二定义标记的位置来计算插值偏移。内插电路可操作地内插位置位置数据并提供内插位置位置数据。

6. 发明授权

US07969337B2 Systems and methods for two tier sampling correction in a data processing circuit 有权
标题翻译：数据处理电路中两层采样校正的系统和方法
公开(公告)号：US07969337B2
公开(公告)日：2011-06-28
申请号：US12510222
申请日：2009-07-27
申请人： Nayak Ratnakar Aravind , James A. Bailey , Robert H. Leonowich
发明人： Nayak Ratnakar Aravind , James A. Bailey , Robert H. Leonowich
IPC分类号： H03M1/00
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/10296 , G11B20/10481 , G11B20/1403 , G11B2220/2516 , H03L7/0807 , H03L7/091 , H04J3/1694 , H04L7/0029 , H04L7/0062
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括模数转换器，数字内插电路，相位误差电路和相位调整控制电路的数据处理电路。模拟数字转换器以至少部分由粗略控制的采样相位对模拟数据输入进行采样，并提供一系列数字采样。数字插值电路至少部分地基于精细控制在数字样本系列的子集之间内插。相位误差电路计算相位误差值。相位调整控制电路可操作以至少部分地基于相位误差值来确定粗略控制和精细控制。

7. 发明申请

US20100329096A1 Systems and Methods for Hard Disk Drive Data Storage Including Reduced Latency Loop Recovery 有权
标题翻译：用于硬盘驱动器数据存储的系统和方法，包括减少延迟环路恢复
公开(公告)号：US20100329096A1
公开(公告)日：2010-12-30
申请号：US12491179
申请日：2009-06-24
申请人： Nayak Ratnakar Aravind
发明人： Nayak Ratnakar Aravind
IPC分类号： G11B20/10
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes a summation circuit, a data detector circuit, an error feedback circuit, and an error calculation circuit. The summation circuit subtracts a low frequency offset feedback from an input signal to yield a processing output. The data detector circuit applies a data detection algorithm to a derivative of the processing output and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts an interim low frequency offset correction signal from a delayed version of the derivative of the processing output to yield an interim factor. The error calculation circuit generates an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output. In such embodiments, the low frequency offset feedback is derived from the interim low frequency offset correction signal.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，讨论了包括求和电路，数据检测器电路，误差反馈电路和误差计算电路的数据处理电路。求和电路从输入信号中减去低频偏移反馈以产生处理输出。数据检测器电路将数据检测算法应用于处理输出的导数，并提供理想的输出。误差反馈电路包括条件减法电路，其从处理输出的导数的延迟版本有条件地减去临时低频偏移校正信号以产生临时因子。误差计算电路至少部分地基于临时因子和理想输出的导数来产生临时低频偏移校正信号。在这样的实施例中，低频偏移反馈是从临时低频偏移校正信号导出的。

8. 发明授权

US08904070B2 Systems and methods for digital MRA compensation 有权
标题翻译：数字MRA补偿的系统和方法
公开(公告)号：US08904070B2
公开(公告)日：2014-12-02
申请号：US13362466
申请日：2012-01-31
申请人： Nayak Ratnakar Aravind , Yu Liao , Haitao Xia
发明人： Nayak Ratnakar Aravind , Yu Liao , Haitao Xia
IPC分类号： G06F13/12 , G06F13/38 , H03M1/12
CPC分类号： H03M1/12 , G06F13/385
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，讨论了包括：模数转换器电路和磁阻调节电路的数据处理系统。模数转换器电路可操作以将输入信号转换成对应的数字采样。磁阻调节电路可操作以由于由磁阻头感测而产生校正输出，从而减少数字采样中的信号不对称性。

9. 发明申请

US20130205185A1 Systems and Methods for Low Latency Media Defect Detection 有权
标题翻译：低延迟介质缺陷检测系统与方法
公开(公告)号：US20130205185A1
公开(公告)日：2013-08-08
申请号：US13368599
申请日：2012-02-08
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G06F11/07
CPC分类号： G11B20/10509 , G11B20/10046 , G11B20/10268 , G11B20/10472 , G11B20/1816 , G11B27/36 , G11B2220/2516 , H04L27/0002
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。例如，公开了一种媒体缺陷检测系统，其包括从介质导出的数据输入，快速包络计算电路，其接收数据输入并且基于数据输入提供快速衰减包络值;慢包络计算电路，其接收数据输入并基于数据输入提供慢衰减包络值，以及介质缺陷检测电路。媒体缺陷检测电路接收慢衰减包络值和快速衰减包络值，计算快速衰减包络值与慢衰减包络值的比值，并至少部分地基于比较来确定缺陷输出比值到缺陷阈值。

10. 发明授权

US08139457B2 Systems and methods for low latency media defect detection 有权
标题翻译：用于低延迟介质缺陷检测的系统和方法
公开(公告)号：US08139457B2
公开(公告)日：2012-03-20
申请号：US12236148
申请日：2008-09-23
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G11B20/18
CPC分类号： G11B5/5565 , G11B5/59611 , G11B20/10037 , G11B20/1816 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。例如，公开了一种媒体缺陷检测系统，其包括从介质导出的数据输入，快速包络计算电路，其接收数据输入并且基于数据输入提供快速衰减包络值;慢包络计算电路，其接收数据输入并基于数据输入提供慢衰减包络值，以及介质缺陷检测电路。媒体缺陷检测电路接收慢衰减包络值和快速衰减包络值，计算快速衰减包络值与慢衰减包络值的比值，并至少部分地基于比较来确定缺陷输出比值到缺陷阈值。

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