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1. 发明授权

US08077644B2 Data transfer in a computing device 有权
标题翻译：计算设备中的数据传输
公开(公告)号：US08077644B2
公开(公告)日：2011-12-13
申请号：US11780604
申请日：2007-07-20
申请人： Jinan Lin , Xiaoning Nie , Ralf Itjeshorst , Tilman Giese , Xianming Deng , Denny Brem , Klaus Mott , Tideya Kella
发明人： Jinan Lin , Xiaoning Nie , Ralf Itjeshorst , Tilman Giese , Xianming Deng , Denny Brem , Klaus Mott , Tideya Kella
IPC分类号： H04B7/00
CPC分类号： H04L49/90
摘要： A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.
摘要翻译：计算装置包括具有至少一个输入缓冲器，多个输出缓冲器，数据传送单元和软件控制单元的硬件数据处理单元，该数据传送单元被配置为将数据从输入缓冲器传送到多个输出缓冲器和被配置为控制数据传送单元的软件控制单元。

2. 发明授权

US08046487B2 Method for routing of data packets and routing apparatus 有权
标题翻译：路由数据包和路由设备的方法
公开(公告)号：US08046487B2
公开(公告)日：2011-10-25
申请号：US10524311
申请日：2003-08-05
申请人： Sankar Narayan Jagannathan , Xiaoning Nie , Jinan Lin
发明人： Sankar Narayan Jagannathan , Xiaoning Nie , Jinan Lin
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L69/16 , H04L69/167
摘要： In order to be able to use a smaller routing table (4) and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table (4) so as to find a correspondence between the destination address identifier and one of the entries of the routing table (4). Each entry of the routing table (4) corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier. After having found a correspondence between the destination address identifier and one of the compressed forwarding addresses stored in the routing table (4), a switch (6) of the IP router switches the respective data packet to one of its output links (OUT) which is associated with the respective forwarding address matching the destination address identifier (ADR).
摘要翻译：为了能够使用较小的路由表（4），并且因此降低成本和功耗并提高IP路由器的性能，建议从数据中提取目的地地址标识符（ADR）要由IP路由器转发的数据包，通过使用无损数据压缩算法压缩提取的目的地地址标识符（ADR），并将压缩的目的地地址标识符与存储在路由表（4）中的条目进行比较，以找到目的地地址标识符和路由表（4）的条目之一。路由表（4）的每个条目对应于IP路由器的可能或可用的转发地址，转发地址已经使用与目的地址标识符相同的数据压缩算法进行了压缩。在找到目的地地址标识符与存储在路由表（4）中的一个压缩转发地址之间的对应关系之后，IP路由器的交换机（6）将相应的数据分组切换到其输出链路（OUT）之一，与与目的地地址标识符（ADR）匹配的相应转发地址相关联。

3. 发明申请

US20050193186A1 Heterogeneous parallel multithread processor (HPMT) with shared contexts 有权
标题翻译：具有共享上下文的异构并行多线程处理器（HPMT）
公开(公告)号：US20050193186A1
公开(公告)日：2005-09-01
申请号：US11064795
申请日：2005-02-24
申请人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
发明人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3802 , G06F9/3891
摘要： The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; pε[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; qε[1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; tε[1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).
摘要翻译：本发明涉及具有共享上下文的异构并行多线程处理器（1），所述共享上下文具有多个（M）并行连接的标准处理器根单元类型（2＆lt; p＆gt;; pepsilon [1，...， M]），其中每个相应的标准处理器根单元类型（2P）具有至少一个或多个（K）并联连接的标准处理器根单元（2＆lt; pq＆gt; 用于从各种线程（T）指令执行程序指令的qepsilon [1，...，K]），具有N个本地上下文存储器的每个标准处理器根单元类型（2 > pt ），其中每个缓冲区存储线程当前处理器状态的一部分。多线程处理器（1）还具有多个（N）个全局上下文存储器（3），每个缓冲器存储当前处理器状态的一部分以及线程控制单元（4），其可以将任何标准处理器根单元（2 >）与任何全局上下文存储器（3T）进行连接。

4. 发明申请

US20050129023A1 Method and device for compressing data packets 审中-公开
标题翻译：用于压缩数据包的方法和设备
公开(公告)号：US20050129023A1
公开(公告)日：2005-06-16
申请号：US10987639
申请日：2004-11-12
申请人： Sankar Jagannathan , Jinan Lin , Xiaoning Nie
发明人： Sankar Jagannathan , Jinan Lin , Xiaoning Nie
IPC分类号： H03M7/30 , H04L29/06 , H04L12/56
CPC分类号： H04L69/04 , H03M7/30 , H04L69/16 , H04L69/161 , H04L69/167
摘要： A method for compressing a data packet is proposed, the data packet comprising at least a first data block and a second data block, the first data block referring to the second data block. In the method, the second data block is compressed and it is noted in the data packet that the second data block has been compressed. In one embodiment, the method is suitable for IPv6 data packets, the second data block then being, for example, a routing header.
摘要翻译：提出了一种用于压缩数据分组的方法，所述数据分组包括至少第一数据块和第二数据块，所述第一数据块参考所述第二数据块。在该方法中，第二数据块被压缩，并且在数据分组中注意到第二数据块已被压缩。在一个实施例中，该方法适用于IPv6数据分组，则第二数据块例如是路由报头。

5. 发明授权

US08209523B2 Data moving processor 失效
标题翻译：数据移动处理器
公开(公告)号：US08209523B2
公开(公告)日：2012-06-26
申请号：US12358048
申请日：2009-01-22
申请人： Ulf Nordqvist , Jinan Lin , Xiaoning Nie , Stefan Maier , Siegmar Koeppe
发明人： Ulf Nordqvist , Jinan Lin , Xiaoning Nie , Stefan Maier , Siegmar Koeppe
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/325 , G06F9/3879
摘要： A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.
摘要翻译：数据移动处理器包括耦合到代码获取电路的代码存储器和耦合到代码提取电路的解码电路。地址堆栈被耦合到解码电路并被配置为存储地址数据。通用堆栈耦合到解码电路并且被配置为存储其他数据。数据移动处理器使用通用堆栈中的数据进行计算。数据移动处理器使用来自地址堆栈的地址数据来识别源和目的地存储单元。地址数据可以用于在读或写操作期间驱动存储器的地址线。使用字节码分别控制地址堆栈和通用堆栈。

6. 发明申请

US20090119460A1 Storing Portions of a Data Transfer Descriptor in Cached and Uncached Address Space 审中-公开
标题翻译：在缓存和未缓存的地址空间中存储数据传输描述符的部分
公开(公告)号：US20090119460A1
公开(公告)日：2009-05-07
申请号：US11936309
申请日：2007-11-07
申请人： Jinan Lin , Xiaoning Nie , Stefan Maier
发明人： Jinan Lin , Xiaoning Nie , Stefan Maier
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F2212/1032
摘要： Methods, apparatuses, and software for storing a first portion of a data transfer descriptor in cached address space, and storing a second portion of the data transfer descriptor in uncached address space. Also, methods, apparatuses, and software for reading at least a portion of a data transfer descriptor from cached address space, initiating a memory transfer based on the data transfer descriptor, and storing a parameter indicating a status of the data transfer descriptor in uncached address space.
摘要翻译：用于将数据传输描述符的第一部分存储在高速缓存地址空间中的方法，装置和软件，以及将数据传输描述符的第二部分存储在未被缓存的地址空间中。而且，用于从高速缓存的地址空间读取数据传输描述符的至少一部分的方法，装置和软件，基于数据传输描述符发起存储器传送，以及将指示数据传输描述符的状态的参数存储在未缓存的地址空间。

7. 发明授权

US07457294B2 Circuit and a method for forwarding data packets in a network 有权
标题翻译：电路和在网络中转发数据包的方法
公开(公告)号：US07457294B2
公开(公告)日：2008-11-25
申请号：US11259957
申请日：2005-10-27
申请人： Jinan Lin , Sankamarayan Jagannathan , Xiaoning Nie
发明人： Jinan Lin , Sankamarayan Jagannathan , Xiaoning Nie
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/54
摘要： In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where tε[1, . . . , T] and D is the smallest common multiple of tε[1, . . . , T]. The control device receives data packets, each having a destination address, codes a destination address of a received data packet using the particular coding method to produce a coded key, and compares the coded key on the basis of its key bit length with the coded addresses stored in the corresponding data sub-store block by block in order to forward the respective data packet via an output to the destination address whose associated coded address matches the coded key from the respective received data packet.
摘要翻译：在网络中转发数据分组的方法中，电路包括数据存储器和控制装置。每个数据分组具有目的地址，并且数据存储包括T数据子存储器，用于存储通过特定编码方法根据其精确地一个数据子存储器中其各自的密钥位长度编码的所有网络地址。第t个数据子存储器被分成具有相同数据元素位长度的D个数据元素的块，其中tepsilon [1，...，。。，T]和D是tepsilon的最小公倍数[1，。。。，T]。控制装置接收具有目的地地址的数据包，使用特定的编码方法对接收到的数据包的目的地地址进行编码，生成编码密钥，并将编码密钥根据其密钥位长与编码地址进行比较存储在对应的数据子存储块中，以便经由输出将相应数据分组转发到相关联的编码地址与来自相应接收的数据分组的编码密钥相匹配的目的地地址。

8. 发明申请

US20050160254A1 Multithread processor architecture for triggered thread switching without any clock cycle loss, without any switching program instruction, and without extending the program instruction format 审中-公开
标题翻译：用于触发线程切换的多线程处理器架构，无任何时钟周期丢失，无需任何切换程序指令，也不扩展程序指令格式
公开(公告)号：US20050160254A1
公开(公告)日：2005-07-21
申请号：US11015299
申请日：2004-12-17
申请人： Jinan Lin , Xiaoning Nie
发明人： Jinan Lin , Xiaoning Nie
IPC分类号： G06F9/00 , G06F9/38 , G06F9/40 , G06F9/42 , G06F9/48
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A multithread processor based on the inventive architecture is a clocked multithread processor (1) for data processing of N threads by means of a standard processor root unit (2), wherein a thread Tj which is to be processed at any given time by the standard processor root unit (2) can be switched without any clock cycle loss by means of a switching trigger signal (UTS) to another thread T1, wherein the switching trigger signal (UTS) is generated as a consequence of a program instruction (which is fetched from a program instruction memory (3) and implies a latency time) for the thread Tj which is to be processed at that time and results in a latency time for the standard processor root unit (2), before the program instruction which has been fetched and implies a latency time is decoded by the standard processor root unit (2).
摘要翻译：基于本发明的架构的多线程处理器是用于通过标准处理器根单元（2）对N个线程进行数据处理的时钟多线程处理器（1），其中将要存在的线程T j 在任何给定时间由标准处理器根单元（2）处理的数据可以通过切换触发信号（UTS）被切换而没有任何时钟周期损失到另一个线程T 1，其中切换触发信号（UTS）作为程序指令（其从程序指令存储器（3）中提取并且暗示延迟时间）的结果而产生，该程序指令将在该时间被处理的线程T 并且在被取出并且暗示延迟时间的程序指令被标准处理器根单元（2）解码之前，导致标准处理器根单元（2）的等待时间。

9. 发明申请

US20050149931A1 Multithread processor architecture for triggered thread switching without any cycle time loss, and without any switching program command 审中-公开
标题翻译：多线程处理器架构，用于触发线程切换，无任何周期时间损失，无需任何切换程序命令
公开(公告)号：US20050149931A1
公开(公告)日：2005-07-07
申请号：US10987215
申请日：2004-11-12
申请人： Jinan Lin , Xiaoning Nie
发明人： Jinan Lin , Xiaoning Nie
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3851 , G06F9/30145
摘要： A multithread processor according to the inventive architecture is a clocked multithread processor for data processing of threads having a standard processor root unit (1) in which threads can be switched to a different thread T1 by means a thread switching trigger data field (11), triggered by the thread Tj which is currently to be processed by the standard processor root unit (1), without any clock cycle loss, with each program instruction Ijk for a thread Tj having a thread switching trigger data field (11) such as this.
摘要翻译：根据本发明的架构的多线程处理器是用于具有标准处理器根单元（1）的线程的数据处理的时钟多线程处理器，其中线程可以通过线程切换到不同的线程1 <1> 切换触发数据字段（11），由当前要由标准处理器根单元（1）处理的线程T SUB> J触发，而没有任何时钟周期损失，每个程序指令I _{jk 。}

10. 发明授权

US07263604B2 Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor type groups and global context memory 有权
标题翻译：具有本地上下文存储器的异构并行多线程处理器（HPMT），用于各自的处理器类型组和全局上下文存储器
公开(公告)号：US07263604B2
公开(公告)日：2007-08-28
申请号：US11064795
申请日：2005-02-24
申请人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
发明人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3802 , G06F9/3891
摘要： The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p∈ [1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q∈ [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t∈ [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).
摘要翻译：本发明涉及一种具有共享上下文的异构并行多线程处理器（1），其具有多个（M）并行连接的标准处理器根单元类型（2），P∈[1，...，，M]），其中每个相应的标准处理器根单元类型（2P）具有至少一个或多个（K个）并行连接的标准处理器根单位（2个pq < ;q∈[1，...，K]），用于从各种线程（T）执行程序指令的指令，具有N个本地上下文存储器的每个标准处理器根单元类型（2
每个缓冲存储一个线程的当前处理器状态的一部分。多线程处理器（1）还具有多个（N）个全局上下文存储器（3），其中每个缓冲器存储当前处理器的一部分（例如，T∈[1，...，N]）线程控制单元（4），其可以将任何标准处理器根单元（2＆gt; pq）连接到任何全局上下文存储器（3T）。

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