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1. 发明授权

US08080843B2 Nonvolatile memory devices and methods of forming the same 有权
公开(公告)号：US08080843B2
公开(公告)日：2011-12-20
申请号：US13152307
申请日：2011-06-03
申请人： Jin-Taek Park , Won-Seok Jung
发明人： Jin-Taek Park , Won-Seok Jung
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11573 , H01L21/31111 , H01L21/31144 , H01L27/11565
摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.

2. 发明授权

US07977732B2 Nonvolatile memory devices and methods of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US07977732B2
公开(公告)日：2011-07-12
申请号：US12238476
申请日：2008-09-26
申请人： Jin-Taek Park , Won-Seok Jung
发明人： Jin-Taek Park , Won-Seok Jung
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11573 , H01L21/31111 , H01L21/31144 , H01L27/11565
摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.
摘要翻译：提供了非易失性存储器件和形成非易失性存储器件的方法。非易失性存储器件包括限定衬底中的有源区的器件隔离层。非易失性存储器件还包括顺序地设置在有源区上的第一绝缘层，非导电电荷存储图案，第二绝缘层和控制栅极线。电荷存储图案包括水平部分和设置在水平部分的边缘的上部上的突起。

3. 发明授权

US07547942B2 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07547942B2
公开(公告)日：2009-06-16
申请号：US11709816
申请日：2007-02-23
申请人： Sang-Hun Jeon , Chang-Seok Kang , Jung-Dal Choi , Jin-Taek Park , Woong-Hee Sohn , Won-Seok Jung
发明人： Sang-Hun Jeon , Chang-Seok Kang , Jung-Dal Choi , Jin-Taek Park , Woong-Hee Sohn , Won-Seok Jung
IPC分类号： H01L21/00
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L29/518 , H01L29/78
摘要： A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.
摘要翻译：非易失性存储器件包括：包括单元区域和外围电路区域的半导体衬底，单元区域上的单元栅极和外围电路区域上的外围电路栅极，其中，所述单元栅极包括半导体上的电荷存储绝缘层基板，电荷存储绝缘层上的栅极电极和栅电极上的导电层，外围电路栅极包括在半导体基板上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层和欧姆层上的导电层。

4. 发明申请

US20110233650A1 NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20110233650A1
公开(公告)日：2011-09-29
申请号：US13152307
申请日：2011-06-03
申请人： Jin-Taek Park , Won-Seok Jung
发明人： Jin-Taek Park , Won-Seok Jung
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/31111 , H01L21/31144 , H01L27/11565
摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.
摘要翻译：提供了非易失性存储器件和形成非易失性存储器件的方法。非易失性存储器件包括限定衬底中的有源区的器件隔离层。非易失性存储器件还包括顺序地设置在有源区上的第一绝缘层，非导电电荷存储图案，第二绝缘层和控制栅极线。电荷存储图案包括水平部分和设置在水平部分的边缘的上部上的突起。

5. 发明申请

US20080105918A1 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080105918A1
公开(公告)日：2008-05-08
申请号：US11709816
申请日：2007-02-23
申请人： Sang-Hun Jeon , Chang-Seok Kang , Jung-Dal Choi , Jin-Taek Park , Woong-Hee Sohn , Won-Seok Jung
发明人： Sang-Hun Jeon , Chang-Seok Kang , Jung-Dal Choi , Jin-Taek Park , Woong-Hee Sohn , Won-Seok Jung
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L29/518 , H01L29/78
摘要： A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.
摘要翻译：非易失性存储器件包括：包括单元区域和外围电路区域的半导体衬底，单元区域上的单元栅极和外围电路区域上的外围电路栅极，其中，所述单元栅极包括半导体上的电荷存储绝缘层基板，电荷存储绝缘层上的栅极电极和栅电极上的导电层，外围电路栅极包括在半导体基板上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层和欧姆层上的导电层。

6. 发明申请

US20090085096A1 Nonvolatile Memory Devices and Methods of Forming the Same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20090085096A1
公开(公告)日：2009-04-02
申请号：US12238476
申请日：2008-09-26
申请人： Jin-Taek Park , Won-Seok Jung
发明人： Jin-Taek Park , Won-Seok Jung
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11573 , H01L21/31111 , H01L21/31144 , H01L27/11565
摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.
摘要翻译：提供了非易失性存储器件和形成非易失性存储器件的方法。非易失性存储器件包括限定衬底中的有源区的器件隔离层。非易失性存储器件还包括顺序地设置在有源区上的第一绝缘层，非导电电荷存储图案，第二绝缘层和控制栅极线。电荷存储图案包括水平部分和设置在水平部分的边缘的上部上的突起。

7. 发明授权

US5878006A Track cross signal correction apparatus 失效
标题翻译：跟踪交叉信号校正装置
公开(公告)号：US5878006A
公开(公告)日：1999-03-02
申请号：US853749
申请日：1997-05-09
申请人： Won-Seok Jung
发明人： Won-Seok Jung
IPC分类号： G11B20/10 , G11B7/00 , G11B7/005 , G11B7/085
CPC分类号： G11B7/08541
摘要： A track cross signal correction apparatus removes noise components contained in a track cross signal. The apparatus includes mask signal generator for comparing pulse widths of the received track cross signals with threshold values, based on the pulse width of a previous track cross signal. A mask signal is generated according to the comparison result. A corrector outputs a received track cross signal when mask signals are generated from the mask signal generator. The track cross signal correction apparatus accurately performs a track seek operation in a medium such as a CD-ROM which requires high-speed access.
摘要翻译：轨道交叉信号校正装置去除包含在轨道交叉信号中的噪声分量。该装置包括掩模信号发生器，用于基于先前的轨道交叉信号的脉冲宽度，将接收的轨道交叉信号的脉冲宽度与阈值进行比较。根据比较结果生成屏蔽信号。当从掩模信号发生器产生掩蔽信号时，校正器输出接收的轨道交叉信号。轨道交叉信号校正装置在需要高速存取的诸如CD-ROM的介质中精确地执行轨道搜索操作。

8. 发明申请

US20110289284A1 MULTI-PROCESSOR DEVICE AND INTER-PROCESS COMMUNICATION METHOD THEREOF 有权
标题翻译：多处理器设备及其处理间通信方法
公开(公告)号：US20110289284A1
公开(公告)日：2011-11-24
申请号：US13110411
申请日：2011-05-18
申请人： Won-Seok Jung , Wooseok Chang , Hyoung-Jin Yun
发明人： Won-Seok Jung , Wooseok Chang , Hyoung-Jin Yun
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/544
摘要： Provided are a multi-process device and an inter-process communication (IPC) method thereof. The multi-processor device includes a first processor, a second processor, a first memory connected to the first processor, and a second memory connected to the second processor. When an inter-process communication (IPC) operation is performed between the first processor and the second processor, data is exchanged between the first memory and the second memory.
摘要翻译：提供了一种多处理设备及其进程间通信（IPC）方法。多处理器设备包括第一处理器，第二处理器，连接到第一处理器的第一存储器和连接到第二处理器的第二存储器。当在第一处理器和第二处理器之间执行进程间通信（IPC）操作时，在第一存储器和第二存储器之间交换数据。

9. 发明申请

US20160104719A1 Semiconductor Memory Devices and Methods of Fabricating the Same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160104719A1
公开(公告)日：2016-04-14
申请号：US14801430
申请日：2015-07-16
申请人： Won-Seok Jung , Youngok Kim , Jihye Kim , Kyungjoong Joo
发明人： Won-Seok Jung , Youngok Kim , Jihye Kim , Kyungjoong Joo
IPC分类号： H01L27/115 , H01L29/51 , H01L29/423 , H01L23/535
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/1157 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.
摘要翻译：半导体存储器件可以包括沿第一方向布置的堆叠和通过堆叠提供的垂直沟道结构。每个堆叠可以包括交替层叠在基板上的栅电极和绝缘层。每个垂直沟道结构可以包括连接到衬底的半导体图案和连接到半导体图案的垂直沟道图案。每个半导体图案可以具有凹入的侧壁，并且半导体图案可以具有彼此不同的最小宽度。

10. 发明授权

US09274860B2 Multi-processor device and inter-process communication method thereof 有权
标题翻译：多处理器设备及其进程间通信方法
公开(公告)号：US09274860B2
公开(公告)日：2016-03-01
申请号：US13110411
申请日：2011-05-18
申请人： Won-Seok Jung , Wooseok Chang , Hyoung-Jin Yun
发明人： Won-Seok Jung , Wooseok Chang , Hyoung-Jin Yun
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F9/54
CPC分类号： G06F9/544
摘要： Provided are a multi-process device and an inter-process communication (IPC) method thereof. The multi-processor device includes a first processor, a second processor, a first memory connected to the first processor, and a second memory connected to the second processor. When an inter-process communication (IPC) operation is performed between the first processor and the second processor, data is exchanged between the first memory and the second memory.
摘要翻译：提供了一种多处理设备及其进程间通信（IPC）方法。多处理器设备包括第一处理器，第二处理器，连接到第一处理器的第一存储器和连接到第二处理器的第二存储器。当在第一处理器和第二处理器之间执行进程间通信（IPC）操作时，在第一存储器和第二存储器之间交换数据。

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