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1. 发明授权

US07246562B2 Structure of delivery door having anti-theft security means 失效
标题翻译：具有防盗保护装置的输送门结构
公开(公告)号：US07246562B2
公开(公告)日：2007-07-24
申请号：US10449041
申请日：2003-05-29
申请人： Jin-Kook Lee , Sung-Hae Lee
发明人： Jin-Kook Lee , Sung-Hae Lee
IPC分类号： E05B7/32
CPC分类号： E06B7/32 , E05G7/007
摘要： The present invention relates to a delivery door having anti-theft security means, more particularly to a door structure consists of a pair of casings, area adjustable mounting plate, hinge means and actuation means, which are installed on an entrance door or a window for delivering articles or products thereof. A delivery door installed on an entrance door or a window comprise an outer casing (4) and an inner casing (5) pivotally mounted on hinge means (3, 8, 9, 10), actuation means (12, 13, 15, 16) associated with the outer casing (4) and the inner casing (5) for opening and closing operation of casings and the mounting plate (6) having area adjustable means between the outer casing (4) and the inner casing (5) is characterized in that the mounting plate (6) is rotatable while in the transporting operation which securely controlled by the actuation means.
摘要翻译：本发明涉及一种具有防盗安全装置的输送门，更具体地涉及一种门结构，其由一对壳体，区域可调安装板，铰链装置和致动装置组成，其安装在入口门或窗户上交付物品或其产品。安装在入口门或窗户上的输送门包括外壳（4）和枢转地安装在铰链装置（3,8,9,10）上的内壳体（5），致动装置（12,13,15,16））与壳体（4）相关联的内壳（5）和壳体的打开和关闭操作以及在外壳（4）和内壳体（5）之间具有区域可调整装置的安装板（6）的特征在于因为安装板（6）在通过致动装置可靠地控制的输送操作中是可旋转的。

2. 发明授权

US07473959B2 Non-volatile semiconductor memory devices and methods of fabricating the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07473959B2
公开(公告)日：2009-01-06
申请号：US11601505
申请日：2006-11-17
申请人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
发明人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/115 , H01L29/513
摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的相关方法。非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。高电介质膜相对于电荷俘获层具有第一势垒。阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。阻挡绝缘膜的厚度在约5至约15的范围内。

3. 发明申请

US20100187595A1 NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100187595A1
公开(公告)日：2010-07-29
申请号：US12694655
申请日：2010-01-27
申请人： Sung-Hae Lee , Byong-Sun Ju , Suk-Jin Chung , Young-Sun Kim
发明人： Sung-Hae Lee , Byong-Sun Ju , Suk-Jin Chung , Young-Sun Kim
IPC分类号： H01L29/788 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324
摘要： Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.
摘要翻译：提供了非易失性存储器件及其制造方法。非易失性存储器件包括衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的栅极间电介质层结构以及栅极间电介质层结构上的控制栅极。栅极间电介质层结构包括第一氧化硅层，第一氧化硅层上的高电介质层和与第一氧化硅层相对的高电介质层上的第二氧化硅层。高电介质层可以包括第一氧化硅层和第二高介电层彼此层叠，并且第一高介电层可以具有比第二高介电层更低的电子陷阱位置密度，并且可以具有比第二高介电层更大的能带隙或导带偏移。

4. 发明申请

US20070007583A1 Gate structure and related non-volatile memory device and method 审中-公开
标题翻译：门结构及相关非易失性存储器件及方法
公开(公告)号：US20070007583A1
公开(公告)日：2007-01-11
申请号：US11474429
申请日：2006-06-26
申请人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Jin-Tae Noh
发明人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Jin-Tae Noh
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L29/40117
摘要： A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The single electrode is formed on the charge trap insulator, comprises a P-type impurity receptive semiconductor material, and is doped with P-type impurities.
摘要翻译：公开了一种适用于SONOS设备单元的门结构。栅极结构包括电荷阱绝缘体和单个电极。电荷陷阱绝缘体包括包含第一氧化硅层，氮化硅层和第二氧化硅层的多层结构。单电极形成在电荷陷阱绝缘子上，包含P型杂质受体半导体材料，并掺杂有P型杂质。

5. 发明授权

US08497555B2 Vertical memory devices including indium and/or gallium channel doping 有权
标题翻译：垂直存储器件包括铟和/或镓通道掺杂
公开(公告)号：US08497555B2
公开(公告)日：2013-07-30
申请号：US13298728
申请日：2011-11-17
申请人： Jin-Gyun Kim , Ki-Hyun Hwang , Sung-Hae Lee , Ji-Hoon Choi
发明人： Jin-Gyun Kim , Ki-Hyun Hwang , Sung-Hae Lee , Ji-Hoon Choi
IPC分类号： H01L29/792 , G11C11/40
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/1041 , H01L29/167 , H01L29/7923
摘要： A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.
摘要翻译：垂直存储器件可以包括衬底，衬底上的第一选择线，第一选择线上的多个字线，多个字线上的第二选择线，以及半导体沟道。第一选择线可以在多个字线和衬底之间，并且多个字线可以在第一和第二选择线之间。此外，第一选择线和第二选择线和多个字线可以在与衬底的表面垂直的方向上间隔开。半导体通道可以延伸离开衬底的与第一和第二选择线和多个字线的侧壁相邻的表面。此外，与第二选择线相邻的半导体通道的部分可以掺杂铟和/或镓。还讨论了相关方法。

6. 发明申请

US20070042573A1 Methods of Forming Conductive Polysilicon Thin Films Via Atomic Layer Deposition and Methods of Manufacturing Semiconductor Devices Including Such Polysilicon Thin Films 有权
标题翻译：通过原子层沉积形成导电多晶硅薄膜的方法和制造包括这种多晶硅薄膜的半导体器件的方法
公开(公告)号：US20070042573A1
公开(公告)日：2007-02-22
申请号：US11421111
申请日：2006-05-31
申请人： Jin-Gyun Kim , Ki-Hyun Hwang , Jin-Tae Noh , Hong-Suk Kim , Sung-Hae Lee
发明人： Jin-Gyun Kim , Ki-Hyun Hwang , Jin-Tae Noh , Hong-Suk Kim , Sung-Hae Lee
IPC分类号： H01L21/20
CPC分类号： H01L27/11521 , C23C16/24 , C23C16/45527 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/28273 , H01L21/28525 , H01L27/115 , H01L29/66825
摘要： A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.
摘要翻译：提供一种形成导电多晶硅薄膜的方法和使用其制造半导体器件的方法。形成导电多晶硅薄膜的方法可以包括同时向衬底提供具有卤素元素的Si前体作为第一反应物和掺杂剂以形成在衬底上掺杂杂质的第一反应物吸附层，然后提供第二反应物对第一反应物吸附层具有H（氢）以使第二反应物的H与第一反应物的卤素元素反应，以在衬底上形成掺杂的Si原子层。

7. 发明申请

US20050148201A1 Method for forming a low-k dielectric layer for a semiconductor device 有权
标题翻译：用于形成半导体器件的低k电介质层的方法
公开(公告)号：US20050148201A1
公开(公告)日：2005-07-07
申请号：US10981731
申请日：2004-11-05
申请人： Jae-Young Ahn , Jin-Gyun Kim , Hee-Seok Kim , Jin-Tae No , Sang-Ryol Yang , Sung-Hae Lee , Hong-Suk Kim , Ju-Wan Lim , Young-Seok Kim , Yong-Woo Hyung , Man-Sug Kang
发明人： Jae-Young Ahn , Jin-Gyun Kim , Hee-Seok Kim , Jin-Tae No , Sang-Ryol Yang , Sung-Hae Lee , Hong-Suk Kim , Ju-Wan Lim , Young-Seok Kim , Yong-Woo Hyung , Man-Sug Kang
IPC分类号： C23C16/30 , C23C16/44 , C23C16/455 , H01L21/318 , H01L21/321 , H01L21/44
CPC分类号： H01L21/0228 , C23C16/30 , C23C16/45531 , H01L21/02274 , H01L21/318 , H01L21/3185 , H01L21/3211
摘要： A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.
摘要翻译：一种用于使用ALD工艺形成用于半导体器件的低k电介质层的方法，包括（a）在半导体衬底上形成预定的互连图案，（b）向其中具有衬底的室提供第一和第二反应性材料，从而将第一和第二反应性材料吸附在衬底的表面上，（c）向腔室供应第一气体以清除保留未反应的第一和第二反应性材料，（d）向室提供第三反应性材料，从而引起所述第一和第二材料和所述第三反应性材料之间的反应以形成单层，（e）向所述室供应第二气体以吹扫在所述室中保留未反应的第三反应性材料和副产物; 和（f）重复（b）至（e）预定次数以在基板上形成具有预定厚度的SiBN三元层。

8. 发明授权

US08264026B2 Nonvolatile memory devices and methods of manufacturing the same 失效
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08264026B2
公开(公告)日：2012-09-11
申请号：US12694655
申请日：2010-01-27
申请人： Sung-Hae Lee , Byong-Sun Ju , Suk-Jin Chung , Young-Sun Kim
发明人： Sung-Hae Lee , Byong-Sun Ju , Suk-Jin Chung , Young-Sun Kim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324
摘要： Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.
摘要翻译：提供了非易失性存储器件及其制造方法。非易失性存储器件包括衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的栅极间电介质层结构以及栅极间电介质层结构上的控制栅极。栅极间电介质层结构包括第一氧化硅层，第一氧化硅层上的高电介质层和与第一氧化硅层相对的高电介质层上的第二氧化硅层。高电介质层可以包括第一氧化硅层和第二高介电层彼此层叠，并且第一高介电层可以具有比第二高介电层更低的电子陷阱位置密度，并且可以具有比第二高介电层更大的能带隙或导带偏移。

9. 发明授权

US07759192B2 Semiconductor device including capacitor and method of fabricating same 失效
标题翻译：包括电容器的半导体器件及其制造方法
公开(公告)号：US07759192B2
公开(公告)日：2010-07-20
申请号：US11258619
申请日：2005-10-24
申请人： Jae-Young Ahn , Jin-Tae Noh , Hee-Seok Kim , Jin-Gyun Kim , Ju-Wan Lim , Sang-Ryol Yang , Hong-Suk Kim , Sung-Hae Lee
发明人： Jae-Young Ahn , Jin-Tae Noh , Hee-Seok Kim , Jin-Gyun Kim , Ju-Wan Lim , Sang-Ryol Yang , Hong-Suk Kim , Sung-Hae Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L28/60 , H01L28/91
摘要： A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.
摘要翻译：半导体器件包括具有底部电极的电容器，形成在底部电极上的电介质层，形成在电介质层上的顶部电极和具有与顶部电极连接的金属的接触插塞，其中顶部电极包括掺杂多晶Si1-xGex层和外延沉积在掺杂多晶Si1-xGex层上的掺杂多晶硅层和接触插塞与掺杂多晶硅层接触。

10. 发明申请

US20070063265A1 Non-volatile semiconductor memory devices and methods of fabricating the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070063265A1
公开(公告)日：2007-03-22
申请号：US11601505
申请日：2006-11-17
申请人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
发明人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/115 , H01L29/513
摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的相关方法。非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。高电介质膜相对于电荷俘获层具有第一势垒。阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。阻挡绝缘膜的厚度在约5至约15的范围内。

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