专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5737362A Delay-locked loop code tracking system for receiver of a code spread communication system 失效
标题翻译：用于码分散通信系统接收机的延迟锁定循环码跟踪系统
公开(公告)号：US5737362A
公开(公告)日：1998-04-07
申请号：US684790
申请日：1996-07-22
申请人： Jin-Il Hyun , In Kang , Jin-Jong Cha , Jae-Seok Kim , Kyung-Soo Kim
发明人： Jin-Il Hyun , In Kang , Jin-Jong Cha , Jae-Seok Kim , Kyung-Soo Kim
IPC分类号： H04B1/7085 , H04L27/30
CPC分类号： H04B1/7085 , Y10S331/02
摘要： The present invention provides a double delay-locked loop(DDLL) code tracking loop for spreading a linear section of an energy detecting area of the tracking loop by using several code time, and provides a delay-locked loop code tracking system for a receiver of a code spread communication system capable of performing an effective code tracking even when a changing ratio of a receiving path is large, by variably using a difference of a preceding time code and a delayed time code according to a change of a receiving environment being changed without cease. Accordingly, the code tracking loop of the present invention improves the receiver performance of the code spread radio communication system, and simplifies a structure of the receiver.
摘要翻译：本发明提供了一种双延迟锁定环路（DDLL）码跟踪环路，用于通过使用多个码时间来扩展跟踪环路的能量检测区域的线性区段，并为接收机提供延迟锁定环路码跟踪系统即使当接收路径的变化率大时也能够通过根据接收环境的变化可变地使用前一时间码和延迟时间码的差异而能够执行有效代码跟踪的码扩展通信系统，而不改变停止。因此，本发明的代码追踪循环改进了代码扩展无线电通信系统的接收机性能，并且简化了接收机的结构。

2. 发明授权

US5726925A Hadamard transformer using memory cell 失效
标题翻译： Hadamard变压器采用存储单元
公开(公告)号：US5726925A
公开(公告)日：1998-03-10
申请号：US557275
申请日：1995-11-14
申请人： Jin-Il Hyun , Jin-Jong Cha , In Kang
发明人： Jin-Il Hyun , Jin-Jong Cha , In Kang
IPC分类号： G06F17/14 , G06F7/36
CPC分类号： G06F17/14
摘要： A Hadamard transformer is disclosed which uses memory cells in a digital signal processor for restoring to the original signals at a receiving end from the signals which have been transformed to a Hadamard function sequenced at a transmitting end. The Hadamard transformer using memory cells includes a counter which receives sample data clocks to output counted signals to a memory address generator and to a plurality of adder/subtractors. The plurality of adder/subtractors add and subtract the input signals and the data read from a memory in accordance with the counted signals of the counter so as to write or record the results into the memory. The memory address generator generates memory addresses in accordance with the sample data clock and the counted signals so that the memory can be read and written to. The memory thus stores the data inputted and outputted to and from the plurality of sadder/subtractors in accordance with the memory addresses generated by the memory address generator. A comparitor compares the final output values of the adder/subtractors at each period of the Hadamard function sequence so as to detect the maximum likelihood of a Hadamard function sequence.
摘要翻译：公开了一种使用数字信号处理器中的存储器单元从接收端恢复原始信号的Hadamard变换器，该信号已被转换为在发送端排序的Hadamard函数。使用存储单元的Hadamard变压器包括接收采样数据时钟以将计数信号输出到存储器地址发生器和多个加法器/减法器的计数器。多个加法器/减法器根据计数器的计数信号对输入信号和从存储器读取的数据进行加法和减法，以便将结果写入或记录到存储器中。存储器地址发生器根据采样数据时钟和计数信号生成存储器地址，使得可以读取和写入存储器。因此，存储器根据由存储器地址发生器产生的存储器地址存储输入和输出多个梯形图/减法器的数据。比较器在Hadamard函数序列的每个周期比较加法器/减法器的最终输出值，以便检测Hadamard函数序列的最大似然。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式