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1. 发明申请

US20090176320A1 METHOD FOR FABRICATION OF FLOATING GATE IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于制造半导体器件中浮动栅的方法
公开(公告)号：US20090176320A1
公开(公告)日：2009-07-09
申请号：US12344504
申请日：2008-12-27
申请人： Jin-Ho Kim , Ki-Min Lee
发明人： Jin-Ho Kim , Ki-Min Lee
IPC分类号： H01L21/66 , H01L21/28 , H01L21/3065
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/28035 , H01L21/32137
摘要： A method for manufacturing a floating gate includes: forming a tunnel oxide film on a semiconductor substrate; forming a polysilicon layer on a surface of the tunnel oxide film; forming a photosensitive film pattern on a surface of the polysilicon layer; depositing a by-product on the photosensitive film to generate a by-product mask; and using the by-product mask as an etching mask to etch the polysilicon layer, completing fabrication of the floating gate. The polysilicon layer may be etched by a simplified process using a by-product mask so as to fabricate the floating gate, the etch rate of the polysilicon layer may be increased to improve productivity, poly bridge problems may be eliminated, and total amount of a gas used in etching the polysilicon layer may be reduced, resulting in an increase in hardware margin and a decrease in the amount of the gas used in this method.
摘要翻译：制造浮栅的方法包括：在半导体衬底上形成隧道氧化膜; 在隧道氧化膜的表面上形成多晶硅层; 在所述多晶硅层的表面上形成感光膜图案; 在感光膜上沉积副产物以产生副产物掩模; 并且使用副产物掩模作为蚀刻掩模来蚀刻多晶硅层，完成浮栅的制造。可以通过使用副产品掩模的简化工艺来蚀刻多晶硅层，以便制造浮栅，可以增加多晶硅层的蚀刻速率以提高生产率，可以消除多桥问题，并且总量用于蚀刻多晶硅层的气体可能会降低，从而导致硬度裕度的增加和在该方法中使用的气体量的减少。

2. 发明申请

US20090273090A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090273090A1
公开(公告)日：2009-11-05
申请号：US12500426
申请日：2009-07-09
申请人： Ki-Min Lee
发明人： Ki-Min Lee
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/3192 , H01L21/76807 , H01L21/7682 , H01L21/76835 , H01L23/5329 , H01L23/53295 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic polymer layer, forming a via hole by sequentially etching the upper porous oxide layer, the pyrolytic polymer layer, and the lower porous oxide layer, forming a trench having a width larger than a width of the via hole by sequentially etching the upper porous oxide layer and the pyrolytic polymer layer in such a manner that the trench is connected with the via hole, forming metal interconnections by filling the via hole and the trench with a metal thin film, and forming a vacuum between the upper and lower porous oxide layers by removing the pyrolytic polymer layer.
摘要翻译：实施例涉及一种半导体器件及其制造方法。实施例可以包括在具有导电层的半导体衬底上形成下多孔氧化物层，在下多孔氧化物层上形成热解聚合物层，在热解聚合物层上形成上部多孔氧化物层，通过依次蚀刻上部多孔氧化物层，热解聚合物层和下部多孔氧化物层，通过依次蚀刻上部多孔氧化物层和热解聚合物层，形成宽度大于通孔宽度的沟槽，沟槽与通孔连接，通过用金属薄膜填充通孔和沟槽形成金属互连，并通过去除热解聚合物层在上部和下部多孔氧化物层之间形成真空。

3. 发明申请

US20090170263A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090170263A1
公开(公告)日：2009-07-02
申请号：US12192085
申请日：2008-08-14
申请人： Ki-Min Lee
发明人： Ki-Min Lee
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42324
摘要： Disclosed is a method of manufacturing a flash memory device. With this method, the surface area of a floating gate is increased by using a buffer film or a dummy pattern, without increasing the size of the flash memory device. Therefore, a coupling ratio is increased, and as a result, programming and erasure speed can be improved.
摘要翻译：公开了一种制造闪速存储器件的方法。利用该方法，通过使用缓冲膜或虚拟图案来增加浮动栅极的表面积，而不增加闪存器件的尺寸。因此，耦合比增加，结果可以提高编程和擦除速度。

4. 发明申请

US20050282348A1 Method of manufacturing thin film capacitor 失效
标题翻译：制造薄膜电容器的方法
公开(公告)号：US20050282348A1
公开(公告)日：2005-12-22
申请号：US11145157
申请日：2005-06-03
申请人： Ki-Min Lee
发明人： Ki-Min Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L27/01 , H01L27/10
CPC分类号： H01L27/016 , H01L28/60
摘要： A first electrode layer having protrusions and depressions on its surface are formed on a lower insulating layer on a semiconductor substrate, and a sacrificial layer is formed on the first electrode layer with a material that is reflowable when heated. After reflowing the sacrificial layer by heat treatment, the reflowed sacrificial layer and first electrode layer are etched so that the protrusions of the first electrode layer are curved, and a dielectric layer and a second electrode layer are sequentially formed on the first electrode layer. When manufactured using the above method, a thin film capacitor may have higher capacitance without increasing the area of the electrode.
摘要翻译：在半导体衬底上的下绝缘层上形成在其表面上具有突起和凹陷的第一电极层，并且在第一电极层上形成具有可加热材料的牺牲层。在通过热处理回流牺牲层之后，蚀刻回流牺牲层和第一电极层，使得第一电极层的突起弯曲，并且在第一电极层上依次形成电介质层和第二电极层。当使用上述方法制造时，薄膜电容器可以具有更高的电容，而不增加电极的面积。

5. 发明申请

US20050032300A1 Methods of manufacturing metal-insulator-metal capacitors of high capacitance in semiconductor devices 审中-公开
标题翻译：制造半导体器件中高电容的金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US20050032300A1
公开(公告)日：2005-02-10
申请号：US10750489
申请日：2003-12-31
申请人： Ki-Min Lee
发明人： Ki-Min Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/65 , H01L28/90
摘要： In accordance with an example process for fabricating an MIM capacitor of high capacitance in a semiconductor device, an interlayer dielectric film is deposited on a metal line and etched to form an MIM capacitor forming region. The lower electrode, the insulator and the upper electrode are sequentially deposited on the interlayer dielectric film, and then etched to from an MIM capacitor.
摘要翻译：根据在半导体器件中制造高电容的MIM电容器的示例性工艺，在金属线上沉积层间电介质膜并进行蚀刻以形成MIM电容器形成区域。下电极，绝缘体和上电极依次沉积在层间电介质膜上，然后从MIM电容器蚀刻。

6. 发明授权

US07541254B2 Method of manufacturing thin film capacitor 失效
标题翻译：制造薄膜电容器的方法
公开(公告)号：US07541254B2
公开(公告)日：2009-06-02
申请号：US11145157
申请日：2005-06-03
申请人： Ki-Min Lee
发明人： Ki-Min Lee
IPC分类号： H01L27/10
CPC分类号： H01L27/016 , H01L28/60
摘要： A first electrode layer having protrusions and depressions on its surface are formed on a lower insulating layer on a semiconductor substrate, and a sacrificial layer is formed on the first electrode layer with a material that is reflowable when heated. After reflowing the sacrificial layer by heat treatment, the reflowed sacrificial layer and first electrode layer are etched so that the protrusions of the first electrode layer are curved, and a dielectric layer and a second electrode layer are sequentially formed on the first electrode layer. When manufactured using the above method, a thin film capacitor may have higher capacitance without increasing the area of the electrode.
摘要翻译：在半导体衬底上的下绝缘层上形成在其表面上具有突起和凹陷的第一电极层，并且在第一电极层上形成具有可加热材料的牺牲层。在通过热处理回流牺牲层之后，蚀刻回流牺牲层和第一电极层，使得第一电极层的突起弯曲，并且在第一电极层上依次形成电介质层和第二电极层。当使用上述方法制造时，薄膜电容器可以具有更高的电容，而不增加电极的面积。

7. 发明授权

US06958278B2 Semiconductor devices and methods for fabricating the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06958278B2
公开(公告)日：2005-10-25
申请号：US10746801
申请日：2003-12-26
申请人： Ki-Min Lee
发明人： Ki-Min Lee
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823462 , H01L29/66545 , Y10S438/981
摘要： Semiconductor devices having a dual gate and method for fabricating the same are disclosed. A disclosed example method comprises: forming dummy gates in a semiconductor substrate; sequentially forming a lightly doped drain (LDD) region, a spacer and a source/drain; depositing an insulation film above the semiconductor substrate; exposing the dummy gates by planarizing the insulation film; removing the dummy gates; selectively injecting impurities into a region associated with at least one of the removed dummy gates; forming gate oxide films having different thicknesses on the regions associated with the removed dummy gates; depositing a polysilicon layer above the gate oxide films; and then forming polysilicon gates by planarizing the polysilicon layer.
摘要翻译：公开了具有双栅极的半导体器件及其制造方法。公开的示例方法包括：在半导体衬底中形成伪栅极; 顺序地形成轻掺杂漏极（LDD）区域，间隔物和源极/漏极; 在半导体衬底上沉积绝缘膜; 通过使绝缘膜平坦化来暴露伪栅极; 去除虚拟门; 选择性地将杂质注入到与去除的虚拟门中的至少一个相关联的区域中; 在与去除的虚拟栅极相关联的区域上形成具有不同厚度的栅极氧化膜; 在栅极氧化膜上沉积多晶硅层; 然后通过平坦化多晶硅层形成多晶硅栅极。

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