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1. 发明授权

US08129264B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08129264B2
公开(公告)日：2012-03-06
申请号：US12181166
申请日：2008-07-28
申请人： Jin-Gyun Kim , Bon-young Koo , Ki-hyun Hwang
发明人： Jin-Gyun Kim , Bon-young Koo , Ki-hyun Hwang
IPC分类号： H01L21/4763
CPC分类号： H01L29/4991 , C23C16/402 , H01L21/02126 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/28273 , H01L21/28282 , H01L21/31629 , H01L21/31633 , H01L21/3185 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/4983
摘要： A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
摘要翻译：提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙方法。

2. 发明授权

US08563421B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08563421B2
公开(公告)日：2013-10-22
申请号：US13363673
申请日：2012-02-01
申请人： Jin-Gyun Kim , Bon-young Koo , Ki-hyun Hwang
发明人： Jin-Gyun Kim , Bon-young Koo , Ki-hyun Hwang
IPC分类号： H01L21/4763
CPC分类号： H01L29/4991 , C23C16/402 , H01L21/02126 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/28273 , H01L21/28282 , H01L21/31629 , H01L21/31633 , H01L21/3185 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/4983
摘要： A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
摘要翻译：提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙方法。

3. 发明授权

US08994091B2 Non-volatile memory device having a vertical structure and method of fabricating the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其制造方法
公开(公告)号：US08994091B2
公开(公告)日：2015-03-31
申请号：US13458293
申请日：2012-04-27
申请人： Sang-Hoon Lee , Jin-Gyun Kim , Koong-Hyun Nam , Ki-Hyun Hwang , Hun-Hyeong Lim , Dong-Kyum Kim
发明人： Sang-Hoon Lee , Jin-Gyun Kim , Koong-Hyun Nam , Ki-Hyun Hwang , Hun-Hyeong Lim , Dong-Kyum Kim
IPC分类号： H01L29/76 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/4234 , H01L29/7889 , H01L29/7926
摘要： A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.
摘要翻译：具有垂直结构的非易失性存储器件包括半导体层，在半导体层上沿垂直方向延伸的侧壁绝缘层，并且具有一个或多个突出区域，在半导体层上沿垂直方向布置的第一控制栅电极并且分别接触在半导体层上形成有一个或多个突起区域的侧壁绝缘层的一部分和在垂直方向上排列的第二控制栅电极，并分别接触一个或多个突出区域中的一个。

4. 发明申请

US20130032878A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130032878A1
公开(公告)日：2013-02-07
申请号：US13560022
申请日：2012-07-27
申请人： Bi-O Kim , Byong-Ju Kim , Jung-Geun Jee , Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Byong-Ju Kim , Jung-Geun Jee , Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/78 , H01L29/02
CPC分类号： H01L27/1157 , H01L27/11582 , H01L29/105
摘要： According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.
摘要翻译：根据示例性实施例，半导体器件包括堆叠在衬底上的水平图案。水平图案通过水平图案定义开口。第一个核心模式是在开幕。第一个核心模式是第一个核心模式的开放。第一活动模式在第一芯图案和水平图案之间。包含第一元件的第二活动图案位于第二芯图案和水平图案之间。第二活性图案含有比第二芯图案中的第一元素的浓度高的浓度的第一元素。

5. 发明申请

US20070042548A1 Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ALD dopant layers and floating gates so formed 审中-公开
标题翻译：在非易失性存储器件中形成浮置栅极的方法包括如此形成的非晶硅和ALD掺杂剂层的交替层和浮置栅极
公开(公告)号：US20070042548A1
公开(公告)日：2007-02-22
申请号：US11496177
申请日：2006-07-31
申请人： Jin-Tae Noh , Ki-Hyun Hwang , Jae-Young Ahn , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae Noh , Ki-Hyun Hwang , Jae-Young Ahn , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/157 , H01L27/115 , H01L27/11521
摘要： A method of forming a silicon layer on a substrate includes providing a silicon source gas to form an amorphous silicon layer on a substrate and providing a dopant source gas to adsorb dopants onto the amorphous silicon layer to form a dopant layer on a surface of the amorphous silicon layer. Related floating gates are also disclosed.
摘要翻译：在衬底上形成硅层的方法包括提供硅源气体以在衬底上形成非晶硅层，并提供掺杂剂源气体以将掺杂剂吸附到非晶硅层上以在无定形的表面上形成掺杂剂层硅层。相关浮动门也被披露。

6. 发明申请

US20070023815A1 Non-volatile memory device and associated method of manufacture 审中-公开
标题翻译：非易失性存储器件及相关制造方法
公开(公告)号：US20070023815A1
公开(公告)日：2007-02-01
申请号：US11493605
申请日：2006-07-27
申请人： Dong-Yean Oh , Jeong-Hyuk Choi , Jai-Hyuk Song , Jong-Kwang Lim , Jae-Young Ahn , Ki-Hyun Hwang , Jin-Gyun Kim , Hong-Suk Kim
发明人： Dong-Yean Oh , Jeong-Hyuk Choi , Jai-Hyuk Song , Jong-Kwang Lim , Jae-Young Ahn , Ki-Hyun Hwang , Jin-Gyun Kim , Hong-Suk Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42336
摘要： A non-volatile memory device comprises a floating gate formed across an active region of a semiconductor substrate, and a control gate electrode formed over the floating gate. An insulation pattern is formed between the floating gate and the active region such that the insulation pattern makes contact with a bottom edge and a sidewall of the floating gate.
摘要翻译：非易失性存储器件包括横跨半导体衬底的有源区域形成的浮置栅极和形成在浮置栅极上的控制栅电极。在浮动栅极和有源区域之间形成绝缘图案，使得绝缘图案与浮动栅极的底部边缘和侧壁接触。

7. 发明授权

US09368646B2 Memory devices and methods of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US09368646B2
公开(公告)日：2016-06-14
申请号：US14182325
申请日：2014-02-18
申请人： Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/792 , H01L29/66
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/66833
摘要： A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.
摘要翻译：垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上顺序地形成在每个沟道的侧壁上。所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

8. 发明授权

US09129857B2 Semiconductor device including a first core pattern under a second core pattern 有权
标题翻译：半导体器件包括在第二芯图案下的第一芯图案
公开(公告)号：US09129857B2
公开(公告)日：2015-09-08
申请号：US13560022
申请日：2012-07-27
申请人： Bi-O Kim , Byong-Ju Kim , Jung-Geun Jee , Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Byong-Ju Kim , Jung-Geun Jee , Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L27/115 , H01L21/336
CPC分类号： H01L27/1157 , H01L27/11582 , H01L29/105
摘要： According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.
摘要翻译：根据示例性实施例，半导体器件包括堆叠在衬底上的水平图案。水平图案通过水平图案定义开口。第一个核心模式是在开幕。第一个核心模式是第一个核心模式的开放。第一活动模式在第一芯图案和水平图案之间。包含第一元件的第二活动图案位于第二芯图案和水平图案之间。第二活性图案含有比第二芯图案中的第一元素的浓度高的浓度的第一元素。

9. 发明授权

US08497555B2 Vertical memory devices including indium and/or gallium channel doping 有权
标题翻译：垂直存储器件包括铟和/或镓通道掺杂
公开(公告)号：US08497555B2
公开(公告)日：2013-07-30
申请号：US13298728
申请日：2011-11-17
申请人： Jin-Gyun Kim , Ki-Hyun Hwang , Sung-Hae Lee , Ji-Hoon Choi
发明人： Jin-Gyun Kim , Ki-Hyun Hwang , Sung-Hae Lee , Ji-Hoon Choi
IPC分类号： H01L29/792 , G11C11/40
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/1041 , H01L29/167 , H01L29/7923
摘要： A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.
摘要翻译：垂直存储器件可以包括衬底，衬底上的第一选择线，第一选择线上的多个字线，多个字线上的第二选择线，以及半导体沟道。第一选择线可以在多个字线和衬底之间，并且多个字线可以在第一和第二选择线之间。此外，第一选择线和第二选择线和多个字线可以在与衬底的表面垂直的方向上间隔开。半导体通道可以延伸离开衬底的与第一和第二选择线和多个字线的侧壁相邻的表面。此外，与第二选择线相邻的半导体通道的部分可以掺杂铟和/或镓。还讨论了相关方法。

10. 发明申请

US20110306195A1 METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 审中-公开
标题翻译：制造垂直半导体器件的方法
公开(公告)号：US20110306195A1
公开(公告)日：2011-12-15
申请号：US13099485
申请日：2011-05-03
申请人： Jin-Gyun Kim , Bo-Young Lee , Ki-Hyun Hwang , Eunkee Hong , Jong-Wan Choi
发明人： Jin-Gyun Kim , Bo-Young Lee , Ki-Hyun Hwang , Eunkee Hong , Jong-Wan Choi
IPC分类号： H01L21/28
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.
摘要翻译：在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。通过牺牲层和绝缘夹层在衬底上形成半导体图案。在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。去除牺牲层图案以在绝缘层间图案之间形成凹槽。凹槽暴露半导体图案的侧壁的部分。在每个槽中形成栅极结构。

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