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1. 发明授权

US08786064B2 Semiconductor package and method for manufacturing the same and semiconductor package module having the same 失效
标题翻译：半导体封装及其制造方法以及具有该封装的半导体封装模块
公开(公告)号：US08786064B2
公开(公告)日：2014-07-22
申请号：US13361144
申请日：2012-01-30
申请人： Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
发明人： Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
IPC分类号： H01L23/495 , H01L21/50 , H01L23/48
CPC分类号： H01L24/83 , H01L23/3121 , H01L23/49503 , H01L23/49513 , H01L23/49524 , H01L23/49531 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/00014 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/18301 , H01L2924/19107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.
摘要翻译：本文公开了一种半导体芯片，包括：在其一个表面上形成有凹部的第一基板和形成在凹部的底表面上的开口; 与第一基板的另一个表面接触的第二基板; 以及安装在凹部中的半导体芯片。

2. 发明申请

US20130105955A1 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME 失效
标题翻译：半导体封装及其制造方法和具有该半导体元件的半导体封装模块
公开(公告)号：US20130105955A1
公开(公告)日：2013-05-02
申请号：US13361144
申请日：2012-01-30
申请人： Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
发明人： Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
IPC分类号： H01L23/495 , H01L21/50 , H01L23/48
CPC分类号： H01L24/83 , H01L23/3121 , H01L23/49503 , H01L23/49513 , H01L23/49524 , H01L23/49531 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/00014 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/18301 , H01L2924/19107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.
摘要翻译：本文公开了一种半导体芯片，包括：在其一个表面上形成有凹部的第一基板和形成在凹部的底表面上的开口; 与第一基板的另一个表面接触的第二基板; 以及安装在凹部中的半导体芯片。

3. 发明申请

US20130147014A1 Wafer Level Package Having Cylindrical Capacitor and Method Of Fabrication The Same 有权
标题翻译：具有圆柱形电容器的晶圆级封装及其制造方法相同
公开(公告)号：US20130147014A1
公开(公告)日：2013-06-13
申请号：US13752238
申请日：2013-01-28
申请人： Seung Seoup Lee , Soon Gyu Yim
发明人： Seung Seoup Lee , Soon Gyu Yim
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L23/3114 , H01L23/5223 , H01L28/90 , H01L2224/131 , H01L2924/01002 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/19041 , H01L2924/014
摘要： Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.
摘要翻译：公开了一种具有圆柱形电容器的晶片级封装，其由于使用圆柱形电容器结构而能够增加静电容量，并且其包括其上形成有焊盘的晶片芯片和形成在其上的绝缘层，并露出焊盘连接到接合焊盘并延伸到绝缘层的一侧的再分配层，连接到再分布层并且具有中心开口的圆筒形外部电极，形成在外部电极的中心开口中的圆柱形内部电极，以便与外部电极分离，形成在外部电极和内部电极之间的电介质层和形成在绝缘层上以覆盖再分配层，内部电极，外部电极和电介质层的树脂密封部分，并且具有用于暴露内部电极的上表面的第一凹部。还提供了一种制造具有圆柱形电容器的晶片级封装的方法。

4. 发明申请

US20100214719A1 CAPACITOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：电容器及其制造方法
公开(公告)号：US20100214719A1
公开(公告)日：2010-08-26
申请号：US12414030
申请日：2009-03-30
申请人： Woon Chun Kim , Sung Yi , Soon Gyu Yim
发明人： Woon Chun Kim , Sung Yi , Soon Gyu Yim
IPC分类号： H01G4/06 , B05D5/12 , H01G4/10
CPC分类号： H01G4/33 , H01G4/10 , H01G4/18 , H01G4/206
摘要： The present invention provides a capacitor including: a bottom electrode; a first dielectric layer formed on the bottom electrode; a conductive polymer layer formed on the first dielectric layer; a second dielectric layer formed on the conductive polymer layer; and a top electrode formed on the second dielectric layer, and a method of manufacturing the same.
摘要翻译：本发明提供一种电容器，包括：底部电极; 形成在所述底部电极上的第一电介质层; 形成在所述第一电介质层上的导电聚合物层; 形成在导电聚合物层上的第二电介质层; 以及形成在第二介电层上的顶电极及其制造方法。

5. 发明申请

US20110115516A1 APPARATUS AND METHOD FOR INSPECTING DEFECTS IN CIRCUIT PATTERN OF SUBSTRATE 失效
标题翻译：用于检查基板电路图中缺陷的装置和方法
公开(公告)号：US20110115516A1
公开(公告)日：2011-05-19
申请号：US12710937
申请日：2010-02-23
申请人： Seung Seoup Lee , Soon Gyu Yim , In Kyung Park
发明人： Seung Seoup Lee , Soon Gyu Yim , In Kyung Park
IPC分类号： G01R31/02
CPC分类号： G01R31/312
摘要： Disclosed herein is an apparatus and method for inspecting defects in the circuit pattern of a substrate. The apparatus for inspecting defects in a circuit pattern of a substrate includes a pin probe configured to input a voltage while coming into contact with an inspection target circuit pattern of a substrate. A capacitor sensor is provided with a membrane electrode which is opposite a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner, and is configured to detect both capacitance and capacitance variation, generated due to displacement of the membrane electrode attributable to electrostatic attractive force acting from the connection circuit pattern on the membrane electrode. A capacitance measurement unit is connected to the capacitor sensor and is configured to measure capacitance attributable to the displacement of the membrane electrode, which is input from the capacitor sensor.
摘要翻译：本文公开了一种用于检查衬底的电路图案中的缺陷的装置和方法。用于检查基板的电路图案中的缺陷的装置包括：引脚探针，其被配置为在与基板的检查对象电路图案接触的同时输入电压。电容器传感器设置有与非接触式电连接到检查对象电路图案的连接电路图案相对的膜电极，并且被配置为检测由于位移而产生的电容和电容变化膜电极归因于从膜电极上的连接电路图案作用的静电吸引力。电容测量单元连接到电容器传感器，并且被配置为测量归因于从电容器传感器输入的膜电极的位移的电容。

6. 发明申请

US20110043363A1 RADIO FREQUENCY IDENTIFICATION TAG, AND METHOD AND MOLD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：无线电频率识别标签及其制造方法和模具
公开(公告)号：US20110043363A1
公开(公告)日：2011-02-24
申请号：US12689011
申请日：2010-01-18
申请人： Woon Chun Kim , Hyun Seop Shim , Woon Bong Joh , Jae Suk Sung , Soon Gyu Yim
发明人： Woon Chun Kim , Hyun Seop Shim , Woon Bong Joh , Jae Suk Sung , Soon Gyu Yim
IPC分类号： G08B13/14
CPC分类号： G06K19/07749
摘要： A radio frequency identification (RFID) tag includes a circuit chip including a pad for an electrical connection on one surface thereof, a molding part receiving the circuit chip therein while exposing the pad to the outside, and an antenna formed on an outer surface of the molding part, having a predetermined pattern shape and electrically connected to the pad.
摘要翻译：射频识别（RFID）标签包括电路芯片，该电路芯片包括在其一个表面上用于电连接的焊盘，在其中将焊盘暴露于外部的同时接收电路芯片的模制部件和形成在外部表面上的天线模制部件，具有预定的图案形状并且电连接到焊盘。

7. 发明申请

US20090321118A1 Printed circuit board embedded chip and manufacturing method thereof 审中-公开
标题翻译：印刷电路板嵌入式芯片及其制造方法
公开(公告)号：US20090321118A1
公开(公告)日：2009-12-31
申请号：US12230874
申请日：2008-09-05
申请人： Woon Chun Kim , Soon Gyu Yim , Joon Seok Kang
发明人： Woon Chun Kim , Soon Gyu Yim , Joon Seok Kang
IPC分类号： H05K1/16 , H05K3/30
CPC分类号： H05K1/0203 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/92144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01075 , H01L2924/01078 , H01L2924/01322 , H01L2924/014 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H01L2924/351 , H05K3/284 , H05K2201/1056 , H05K2201/10674 , Y10T29/4913 , Y10T29/49139 , H01L2924/00
摘要： An electronic component embedded printed circuit board and a manufacturing method thereof. The electronic component embedded printed circuit board includes an insulating layer forming a core layer; an electronic component inserted to project a part thereof on an upper part of the insulating layer; a metallic seed layer formed on the insulating layer including a projected surface of the electronic component; a plating layer formed on the metallic seed layer; circuit patterns electrically connected to pads of the electronic component through via-holes formed on the insulating layer; and a solder resist layer which is formed on the insulating layer and has solder balls attached onto the via-holes electrically connected to the circuit patterns. In the electronic component embedded printed circuit board, a heat radiation characteristic can be maximized and a thickness of the printed circuit board can be minimized. In case that the insulating is made of a thermoplastic resin, the electronic component can be reutilized, thereby saving product cost.
摘要翻译：一种电子部件嵌入式印刷电路板及其制造方法。电子部件嵌入式印刷电路板包括形成芯层的绝缘层; 被插入以将其部分投影在绝缘层的上部上的电子部件; 形成在绝缘层上的金属种子层，包括电子部件的投影表面; 形成在所述金属种子层上的镀层; 电路图案通过形成在绝缘层上的通孔电连接到电子部件的焊盘; 以及阻焊层，其形成在绝缘层上并且具有附着到电连接到电路图案的通孔上的焊球。在电子部件嵌入式印刷电路板中，可以使热辐射特性最大化，并且可以使印刷电路板的厚度最小化。在绝热材料由热塑性树脂制成的情况下，电子部件可以再利用，从而节省产品成本。

8. 发明授权

US08471581B2 Apparatus and method for inspecting defects in circuit pattern of substrate 失效
标题翻译：检测基板电路图形缺陷的装置及方法
公开(公告)号：US08471581B2
公开(公告)日：2013-06-25
申请号：US12710937
申请日：2010-02-23
申请人： Seung Seoup Lee , Soon Gyu Yim , In Kyung Park
发明人： Seung Seoup Lee , Soon Gyu Yim , In Kyung Park
IPC分类号： G01R31/00
CPC分类号： G01R31/312
摘要： Disclosed herein is an apparatus and method for inspecting defects in the circuit pattern of a substrate. The apparatus for inspecting defects in a circuit pattern of a substrate includes a pin probe configured to input a voltage while coming into contact with an inspection target circuit pattern of a substrate. A capacitor sensor is provided with a membrane electrode which is opposite a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner, and is configured to detect both capacitance and capacitance variation, generated due to displacement of the membrane electrode attributable to electrostatic attractive force acting from the connection circuit pattern on the membrane electrode. A capacitance measurement unit is connected to the capacitor sensor and is configured to measure capacitance attributable to the displacement of the membrane electrode, which is input from the capacitor sensor.
摘要翻译：本文公开了一种用于检查衬底的电路图案中的缺陷的装置和方法。用于检查基板的电路图案中的缺陷的装置包括：引脚探针，其被配置为在与基板的检查对象电路图案接触的同时输入电压。电容器传感器设置有与非接触式电连接到检查对象电路图案的连接电路图案相对的膜电极，并且被配置为检测由于位移而产生的电容和电容变化膜电极归因于从膜电极上的连接电路图案作用的静电吸引力。电容测量单元连接到电容器传感器，并且被配置为测量归因于从电容器传感器输入的膜电极的位移的电容。

9. 发明申请

US20110061904A1 Display array substrate and method of manufacturing display substrate 审中-公开
标题翻译：显示阵列基板及制造显示基板的方法
公开(公告)号：US20110061904A1
公开(公告)日：2011-03-17
申请号：US12654369
申请日：2009-12-17
申请人： Woon Chun Kim , Hyun Seop Shim , Soon Gyu Yim , Jong Young Lee
发明人： Woon Chun Kim , Hyun Seop Shim , Soon Gyu Yim , Jong Young Lee
IPC分类号： H05K1/03 , B26D3/06 , B26D9/00
CPC分类号： H05K3/0052 , B26D3/06 , H05K2201/0108 , H05K2201/09036 , H05K2201/0909 , Y10T83/0304 , Y10T83/0524
摘要： A display array substrate according to an aspect of the invention may include: a substrate wafer having cutting grooves curved inward; and a transparent electrode coated over one surface of the substrate wafer, wherein shock, occurring when cutting the substrate wafer, is prevented from being transmitted to the transparent electrode by cutting the substrate wafer along the cutting grooves having a different height from the transparent electrode.
摘要翻译：根据本发明的一个方面的显示阵列基板可以包括：具有向内弯曲的切割槽的基板晶片; 以及在衬底晶片的一个表面上涂覆的透明电极，其中通过沿着与透明电极不同的高度的切割槽切割衬底晶片，防止在切割衬底晶片时发生的冲击而被透射到透明电极。

10. 发明授权

US08656582B2 Method of attaching die using self-assembling monolayer and package substrate including die attached thereto using self-assembling monolayer 有权
标题翻译：使用自组装单层和使用自组装单层附着于其上的模具的封装衬底附接裸片的方法
公开(公告)号：US08656582B2
公开(公告)日：2014-02-25
申请号：US12424494
申请日：2009-04-15
申请人： Seung Seoup Lee , Soon Gyu Yim , Jong Woo Han
发明人： Seung Seoup Lee , Soon Gyu Yim , Jong Woo Han
IPC分类号： H05K3/30 , H01L21/00
CPC分类号： H01L24/95 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/83 , H01L25/0655 , H01L25/50 , H01L2224/83193 , H01L2224/838 , H01L2224/95085 , H01L2224/95146 , H01L2224/95147 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , Y10T29/4913 , Y10T156/10 , H01L2924/00
摘要： Disclosed herein are a method of attaching a die using a self-assembling monolayer and a package substrate including a die attached thereto using a self-assembling monolayer. A first self-assembling monolayer formed on a die and a second self-assembling monolayer formed on a substrate are provided with the same hydrophilic or hydrophobic functional group, so that the die is attached to the substrate using an attractive force acting between the first and second self-assembling monolayers. An accuracy of alignment between the die and the substrate can be improved by the simple solution.
摘要翻译：本文公开了一种使用自组装单层和包含基片的封装衬底附接裸片的方法，所述封装衬底使用自组装单层附着于其上。在模具上形成的第一自组装单层和在基底上形成的第二自组装单层设置有相同的亲水或疏水官能团，使得模具使用在第一和第第二自组装单层。可以通过简单的解决方案来改善管芯和衬底之间的对准精度。

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