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1. 发明申请

US20090146296A1 Method of forming high-k dielectric stop layer for contact hole opening 有权
标题翻译：形成用于接触孔开口的高k电介质停止层的方法
公开(公告)号：US20090146296A1
公开(公告)日：2009-06-11
申请号：US11953881
申请日：2007-12-11
申请人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Chun Hui LOW , Chim Seng SEET , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Chun Hui LOW , Chim Seng SEET , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L21/461 , H01L23/48
CPC分类号： H01L21/76832 , H01L21/76895 , H01L21/76897
摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.
摘要翻译：包括初级和次级阻挡层的复合蚀刻停止层用于在电介质层中形成接触衬底中的区域的接触。次蚀刻停止层包括高k电介质材料，以在接触形成期间与电介质层实现高蚀刻选择性。去除次级停止层以暴露接触区域。通过对材料的高选择性实现二次停止层的去除。

2. 发明申请

US20090289309A1 METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：降低集成电路中硅氧化物缺陷的方法
公开(公告)号：US20090289309A1
公开(公告)日：2009-11-26
申请号：US12124177
申请日：2008-05-21
申请人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

3. 发明申请

US20100267236A1 METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：降低集成电路中硅氧化物缺陷的方法
公开(公告)号：US20100267236A1
公开(公告)日：2010-10-21
申请号：US12825325
申请日：2010-06-28
申请人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

4. 发明申请

US20090250764A1 STRESSED DIELECTRIC LAYER WITH STABLE STRESS 有权
标题翻译：具有稳定应力的应力介电层
公开(公告)号：US20090250764A1
公开(公告)日：2009-10-08
申请号：US12062535
申请日：2008-04-04
申请人： Huang LIU , Jeff SHU , Luona GOH , Wei LU
发明人： Huang LIU , Jeff SHU , Luona GOH , Wei LU
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/665 , H01L29/7843
摘要： An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.
摘要翻译：提供了一种集成电路，其具有衬底和在衬底的有源区域中的晶体管。衬底还具有具有电介质材料的隔离区域。在一个实施例中，预先金属介电层设置在衬底和晶体管的上方。隔离区域或预金属介电层中的至少一个包括具有应力保持掺杂剂的O 3 TEOS氧化物。 O 3 TEOS氧化物在晶体管的沟道区域中引起应力。

5. 发明申请

US20110316085A1 INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS 审中-公开
标题翻译：集成电路，包括具有稳定应力的压电介质层
公开(公告)号：US20110316085A1
公开(公告)日：2011-12-29
申请号：US13225483
申请日：2011-09-05
申请人： Huang LIU , Jeff SHU , Luona GOH , Wei LU
发明人： Huang LIU , Jeff SHU , Luona GOH , Wei LU
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/665 , H01L29/7843
摘要： An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.
摘要翻译：提供了一种集成电路，其具有衬底和在衬底的有源区域中的晶体管。衬底还具有具有电介质材料的隔离区域。在一个实施例中，预先金属介电层设置在衬底和晶体管的上方。隔离区域或预金属介电层中的至少一个包括具有应力保持掺杂剂的O 3 TEOS氧化物。 O 3 TEOS氧化物在晶体管的沟道区域中引起应力。

6. 发明申请

US20100109155A1 RELIABLE INTERCONNECT INTEGRATION 审中-公开
标题翻译：可靠的互连整合
公开(公告)号：US20100109155A1
公开(公告)日：2010-05-06
申请号：US12265714
申请日：2008-11-05
申请人： Huang LIU , Johnny WIDODO , Yihua WANG , Wuping LIU , Ti OUYANG , Wei LU
发明人： Huang LIU , Johnny WIDODO , Yihua WANG , Wuping LIU , Ti OUYANG , Wei LU
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection.
摘要翻译：半导体器件包括其上部被致密化的介电层。互连设置在电介质层中。致密部分在随后的处理期间减少了底切，提高了互连的可靠性。

7. 发明申请

US20090315121A1 STABLE STRESS DIELECTRIC LAYER 审中-公开
标题翻译：稳定应力电介质层
公开(公告)号：US20090315121A1
公开(公告)日：2009-12-24
申请号：US12141932
申请日：2008-06-19
申请人： Luona GOH , Jeff Jiehui SHU , Huang LIU , Wei LU
发明人： Luona GOH , Jeff Jiehui SHU , Huang LIU , Wei LU
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L29/7846 , H01L21/02126 , H01L21/02216 , H01L21/02271 , H01L21/3115 , H01L21/3143 , H01L21/31608 , H01L21/76224 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric (PMD) layer is disposed over the substrate and the transistor. At least one of the isolation region or the PMD layer includes O3-TEOS having a first stress. A cap layer is disposed over the O3-TEOS in the isolation region or the PMD layer. The cap layer prevents degradation of the first stress of the O3-TEOS.
摘要翻译：提供了一种集成电路，其具有衬底和在衬底的有源区域中的晶体管。衬底还具有具有电介质材料的隔离区域。在一个实施例中，在衬底和晶体管上设置预金属电介质（PMD）层。隔离区域或PMD层中的至少一个包括具有第一应力的O3-TEOS。覆盖层设置在隔离区域或PMD层中的O3-TEOS上。盖层防止O3-TEOS的第一应力退化。

8. 发明申请

US20160044508A1 METHOD FOR PROVIDING APPLICATION SERVICE 审中-公开
公开(公告)号：US20160044508A1
公开(公告)日：2016-02-11
申请号：US14886587
申请日：2015-10-19
申请人： Minsheng WANG , Wei LU , Xiaojun LIU , Wuqiang LIN
发明人： Minsheng WANG , Wei LU , Xiaojun LIU , Wuqiang LIN
IPC分类号： H04W12/04 , H04L29/06 , H04W12/06
CPC分类号： H04W12/04 , H04L9/0861 , H04L9/3231 , H04L63/0281 , H04L63/0428 , H04L63/061 , H04L63/0861 , H04L2209/80 , H04L2463/062 , H04W12/02 , H04W12/06 , H04W12/08 , H04W80/12
摘要： A method for providing application service is provided. The method discloses that a user is authenticated according to a received application service acquisition request from a user mobile phone, and when the user authentication is passed, the application service acquisition request is sent to an application server, so that the application server provides an application service to the user mobile phone according to the application service acquisition request. The application server does not need to authenticate the user mobile phone by performing an authentication operation on the user mobile phone through a wireless application protocol gateway, thus being capable of reducing the workload of the application server.

9. 发明申请

US20120166169A1 MODELING TECHNIQUE FOR RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS 有权
标题翻译：电阻随机存取存储器（RRAM）细胞的建模技术
公开(公告)号：US20120166169A1
公开(公告)日：2012-06-28
申请号：US13077941
申请日：2011-03-31
申请人： Wei LU
发明人： Wei LU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5027 , G11C13/0007 , G11C13/0009
摘要： Accurate simulation of two-terminal resistive random access memory (RRAM) behavior is accomplished by solving equations including state variables for filament length growth, filament width growth, and temperature. Such simulations are often run in a SPICE environment. Highly accurate models simulate the dynamic nature of filament propagation and multiple resistive states by using a sub-circuit to represent an RRAM cell. In the sub-circuit, voltages on floating nodes control current output while the voltage dropped across the sub-circuit controls growth and temperature characteristics. Properly executed, such a sub-circuit can accurately model filament growth at all phases of conductance including dynamic switching and a plurality of resistive states.
摘要翻译：两端电阻随机存取存储器（RRAM）行为的精确仿真是通过求解包括灯丝长度生长，灯丝宽度生长和温度的状态变量的方程来实现的。这种模拟通常在SPICE环境中运行。高精度模型通过使用子电路来表示RRAM单元来模拟灯丝传播和多个电阻状态的动态特性。在子电路中，浮动节点上的电压控制电流输出，而跨越子电路的电压控制生长和温度特性。正确地执行，这样的子电路可以在包括动态切换和多个电阻状态的所有电导阶段中精确地模拟长丝生长。

10. 发明申请

US20110266688A1 PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的平面钝化层
公开(公告)号：US20110266688A1
公开(公告)日：2011-11-03
申请号：US13179573
申请日：2011-07-11
申请人： Sin Leng LIM , In Ki KIM , Jong Sung PARK , Min Hwan KIM , Wei LU
发明人： Sin Leng LIM , In Ki KIM , Jong Sung PARK , Min Hwan KIM , Wei LU
IPC分类号： H01L23/48
CPC分类号： G02F1/1333 , G02F1/136277 , G02F2001/133357 , Y10S438/954
摘要： A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
摘要翻译：半导体器件包括在衬底上具有电介质层和器件层的衬底。设备层具有开口。第一和第二子层设置在器件层上并对开口进行排列。第二子层用作平坦化的停止层，以为半导体器件提供基本平坦化的顶表面。

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