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    • 1. 发明授权
    • ESD protection circuit for different power supplies
    • ESD保护电路用于不同电源
    • US06400542B1
    • 2002-06-04
    • US09882680
    • 2001-06-18
    • Jian-Hsing LeeJian-Ren ShihYi-Hsun WuJing-Meng Liu
    • Jian-Hsing LeeJian-Ren ShihYi-Hsun WuJing-Meng Liu
    • H02H900
    • H01L27/0259
    • A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.
    • 一种电压钳位电路,当ESD事件在多个分离的电源电压端子之间引起过大的差分电压时,保护具有多个单独的电源电压端子的集成电路免受损坏。 电压钳位电路有两个Darlington连接钳位晶体管的子组。 达林顿连接的钳位晶体管的第一个子组连接在第一电源电压端子和第二电源电压端子之间。 如果差分电压超过第一钳位电压电平,则达林顿连接的钳位晶体管的第一个子组导通,并将第一个差分电压恢复到小于第一钳位电压电平的电平。 连接在第二电源端子和第一电源端子之间的达林顿的第二子组连接钳位晶体管。 如果差分电压超过第二钳位电压电平,则达林顿连接晶体管的第二个子组导通,并将差分电压恢复到小于第二钳位电压电平的电平。
    • 4. 发明授权
    • ESD protection circuit for different power supplies
    • ESD保护电路用于不同电源
    • US06271999B1
    • 2001-08-07
    • US09196603
    • 1998-11-20
    • Jian-Hsing LeeJiaw-Ren ShihYi-Hsun WuJing-Meng Liu
    • Jian-Hsing LeeJiaw-Ren ShihYi-Hsun WuJing-Meng Liu
    • H02H900
    • H01L27/0259
    • A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.
    • 一种电压钳位电路,当ESD事件在多个分离的电源电压端子之间引起过大的差分电压时,保护具有多个单独的电源电压端子的集成电路免受损坏。 电压钳位电路有两个Darlington连接钳位晶体管的子组。 达林顿连接的钳位晶体管的第一个子组连接在第一电源电压端子和第二电源电压端子之间。 如果差分电压超过第一钳位电压电平,则达林顿连接的钳位晶体管的第一个子组导通,并将第一个差分电压恢复到小于第一钳位电压电平的电平。 连接在第二电源端子和第一电源端子之间的达林顿的第二子组连接钳位晶体管。 如果差分电压超过第二钳位电压电平,则达林顿连接晶体管的第二个子组导通,并将差分电压恢复到小于第二钳位电压电平的电平。
    • 5. 发明授权
    • Displacement current trigger SCR
    • 位移电流触发SCR
    • US06249414B1
    • 2001-06-19
    • US09670404
    • 2000-09-28
    • Jian-Hsing LeeJiaw-Ren ShihYi-Hsun WuJing-Meng Liu
    • Jian-Hsing LeeJiaw-Ren ShihYi-Hsun WuJing-Meng Liu
    • H02H322
    • H01L27/0262H01L29/87
    • Circuits, device structures and methods are disclosed which protect CMOS semiconductor devices, having oxides as thin as 32 Angstrom, from electrostatic discharge (ESD) by utilizing a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device. The protection is afforded by providing low voltage triggering of the parasitic SCR in the order of 1.2 Volt. Triggering at such low voltages is made possible by means of a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.
    • 公开了电路,器件结构和方法,其通过利用半导体器件固有的寄生可控硅整流器(SCR)来保护具有薄至32埃的氧化物的CMOS半导体器件免受静电放电(ESD)的影响。 通过提供大约1.2伏的寄生SCR的低电压触发来提供保护。 借助于使SCR(寄生npn和pnp双极型晶体管)的分量导通(即触发SCR)的位移电流触发,可以在这样的低电压下进行触发。 位移电流由结电容实现,该结电容器在一侧连接到待保护的焊盘,另一侧连接到上述寄生双极晶体管的端子。 公开了实现结电容的两种方式。
    • 6. 发明授权
    • Electrostatic discharge protective circuit for reducing an undesired
channel turn-on
    • 用于减少不需要的通道开启的静电放电保护电路
    • US6008974A
    • 1999-12-28
    • US188178
    • 1998-11-09
    • Jian-Hsing LeeYi-Hsun WuJiaw-Ren ShihJing-Meng Liu
    • Jian-Hsing LeeYi-Hsun WuJiaw-Ren ShihJing-Meng Liu
    • H01L27/02H02H3/22
    • H01L27/0251H01L27/0266
    • An electrostatic discharge (ESD) protective circuit for reducing the electron-tunneling phenomena in NMOS devices. Several complementary metal oxide semiconductor (CMOS) devices act as an ESD protective circuit from being destroyed. The CMOS devices are connected to an internal circuit and a power line provide a bias voltage for the devices. The drains of the CMOS devices are connected to a pad to output a driving current. A NMOS device is connected between the internal circuit and the ESD protective circuit for protecting the NMOS devices in the circuit. As an ESD pulse is input into the ESD protective circuit, the NMOS device is then turned on by the pulse. Thus, positive charges on the gate of the NMOS devices in the ESD circuit is conducted into ground. Therefore, the NMOS device between the internal circuit and the ESD circuit can prevent the gate oxide of the NMOS device in the circuit from damage.
    • 一种用于减少NMOS器件中的电子隧道现象的静电放电(ESD)保护电路。 几种互补金属氧化物半导体(CMOS)器件用作ESD保护电路被破坏。 CMOS器件连接到内部电路,电源线为器件提供偏置电压。 CMOS器件的漏极连接到焊盘以输出驱动电流。 NMOS器件连接在内部电路和ESD保护电路之间,用于保护电路中的NMOS器件。 由于ESD脉冲被输入到ESD保护电路中,NMOS器件然后被脉冲导通。 因此,ESD电路中的NMOS器件的栅极上的正电荷被导通到地。 因此,内部电路和ESD电路之间的NMOS器件可以防止电路中的NMOS器件的栅极氧化物损坏。