会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Hybrid control methods for digital pulse width modulator (DPWM)
    • 数字脉宽调制器(DPWM)的混合控制方法
    • US07570037B2
    • 2009-08-04
    • US11561104
    • 2006-11-17
    • Jian LiDong S. HaYang QiuMing XuFred C. Lee
    • Jian LiDong S. HaYang QiuMing XuFred C. Lee
    • G05F1/575G05F1/618
    • H02M3/157
    • A digital pulse width modulator leverages clock frequency to achieve very fine duty cycle resolution by using a constant number of time slots for each state of a pulse signal and varying the number of time slots in a switching cycle within acceptable limits for variation of the switching cycle frequency or by using two relatively low frequency clocks of slightly differing frequency and selecting pulse leading and trailing edges in accordance with pulses output therefrom. A fine resolution of duty cycle adjustment can thus be provided corresponding to a much higher effective clock frequency than is actually used; allowing improvement of efficiency of clock and switching circuits, particularly in switching voltage regulator applications.
    • 数字脉冲宽度调制器利用时钟频率通过对脉冲信号的每个状态使用恒定数量的时隙来实现非常精细的占空比分辨率,并且在开关周期内将开关周期中的时隙数量改变为可接受的开关周期变化的限度内 或通过使用两个稍微不同频率的相对低频的时钟,并根据从其输出的脉冲选择脉冲前沿和后沿。 因此,可以对应于比实际使用的更高的有效时钟频率提供精确的占空比调整分辨率; 允许提高时钟和开关电路的效率,特别是在开关稳压器应用中。
    • 2. 发明授权
    • Digital power supply control
    • 数字电源控制
    • US07705577B2
    • 2010-04-27
    • US11755331
    • 2007-05-30
    • Jian LiYang QiuMing XuFred C. Lee
    • Jian LiYang QiuMing XuFred C. Lee
    • G05F1/00
    • H02M3/157
    • A switched voltage regulator provides improved regulation at a lower clock rate/sampling frequency (e.g. several orders of magnitude lower than would be required for comparable regulation) while using a low resolution digital pulse width modulator such that limit cycle oscillations occur (and thus of low cost and complexity and small size) by limiting the amplitude of limit cycle oscillations which therefore need not be avoided by more complex arrangements which are not commercially feasible. Limiting of amplitude of limit cycle oscillations is achieved by adding essentially a digitized ripple voltage signal corresponding to the difference between the output of the voltage regulator and an average output of the voltage regulator as an input to the digital pulse width modulator. Performance of this arrangement may be enhanced by adding a ramp signal to the digitized ripple voltage signal and even further enhanced by limiting the ramp signal to a range which corresponds to steady state operation but not transients.
    • 开关电压调节器在使用低分辨率数字脉冲宽度调制器时,以较低的时钟频率/采样频率(例如比可比较的调节要求的数量级低几个数量级)提供改进的调节器,从而发生极限循环振荡(从而降低 成本和复杂性以及小尺寸)通过限制极限循环振荡的幅度,因此不可避免地由于商业上不可行的更复杂的布置。 极限循环振荡幅度的限制通过将基本上相当于电压调节器的输出与调压器的平均输出之间的差值相对应的数字化纹波电压信号作为数字脉宽调制器的输入来实现。 可以通过向数字化纹波电压信号添加斜坡信号并且甚至通过将斜坡信号限制到对应于稳态操作但不是瞬变的范围来进一步增强该布置的性能。
    • 3. 发明申请
    • Digital Constant On-Time Power Supply Control
    • 数字恒定导通时间电源控制
    • US20080298090A1
    • 2008-12-04
    • US11755331
    • 2007-05-30
    • Jian LiYang QiuMing XuFred C. Lee
    • Jian LiYang QiuMing XuFred C. Lee
    • H02M3/335
    • H02M3/157
    • A switched voltage regulator provides improved regulation at a lower clock rate/sampling frequency (e.g. several orders of magnitude lower than would be required for comparable regulation) while using a low resolution digital pulse width modulator such that limit cycle oscillations occur (and thus of low cost and complexity and small size) by limiting the amplitude of limit cycle oscillations which therefore need not be avoided by more complex arrangements which are not commercially feasible. Limiting of amplitude of limit cycle oscillations is achieved by adding essentially a digitized ripple voltage signal corresponding to the difference between the output of the voltage regulator and an average output of the voltage regulator as an input to the digital pulse width modulator. Performance of this arrangement may be enhanced by adding a ramp signal to the digitized ripple voltage signal and even further enhanced by limiting the ramp signal to a range which corresponds to steady state operation but not transients.
    • 开关电压调节器在使用低分辨率数字脉冲宽度调制器时,以较低的时钟频率/采样频率(例如比可比较的调节要求的数量级低几个数量级)提供改进的调节器,从而发生极限循环振荡(从而降低 成本和复杂性以及小尺寸)通过限制极限循环振荡的幅度,因此不可避免地由于商业上不可行的更复杂的布置。 极限循环振荡幅度的限制通过将基本上相当于电压调节器的输出与调压器的平均输出之间的差值相对应的数字化纹波电压信号作为数字脉宽调制器的输入来实现。 可以通过向数字化纹波电压信号添加斜坡信号并且甚至通过将斜坡信号限制到对应于稳态操作但不是瞬变的范围来进一步增强该布置的性能。
    • 4. 发明申请
    • HYBRID CONTROL METHODS FOR DIGITAL PULSE WIDTH MODULATOR (DPWM)
    • 数字脉宽调制器混合控制方法(DPWM)
    • US20080116871A1
    • 2008-05-22
    • US11561104
    • 2006-11-17
    • Jian LiDong S. HaYang QiuMing XuFred C. Lee
    • Jian LiDong S. HaYang QiuMing XuFred C. Lee
    • G05F1/00
    • H02M3/157
    • A digital pulse width modulator leverages clock frequency to achieve very fine duty cycle resolution by using a constant number of time slots for each state of a pulse signal and varying the number of time slots in a switching cycle within acceptable limits for variation of the switching cycle frequency or by using two relatively low frequency clocks of slightly differing frequency and selecting pulse leading and trailing edges in accordance with pulses output therefrom. A fine resolution of duty cycle adjustment can thus be provided corresponding to a much higher effective clock frequency than is actually used; allowing improvement of efficiency of clock and switching circuits, particularly in switching voltage regulator applications.
    • 数字脉冲宽度调制器利用时钟频率通过对脉冲信号的每个状态使用恒定数量的时隙来实现非常精细的占空比分辨率,并且在开关周期内将开关周期中的时隙数量改变为可接受的开关周期变化的限度内 或通过使用两个稍微不同频率的相对低频的时钟,并根据从其输出的脉冲选择脉冲前沿和后沿。 因此,可以对应于比实际使用的更高的有效时钟频率提供精确的占空比调整分辨率; 允许提高时钟和开关电路的效率,特别是在开关稳压器应用中。