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1. 发明授权

US09176862B2 SLC-MLC wear balancing 有权
标题翻译： SLC-MLC磨损平衡
公开(公告)号：US09176862B2
公开(公告)日：2015-11-03
申请号：US13340446
申请日：2011-12-29
申请人： Jian Chen , Sergey Anatolievich Gorobets , Steven Sprouse
发明人： Jian Chen , Sergey Anatolievich Gorobets , Steven Sprouse
IPC分类号： G06F12/00 , G06F12/02 , G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： A method and system for SLC-MLC Wear Balancing in a flash memory device is disclosed. The flash memory device includes a single level cell (SLC) portion and a multi-level cell (MLC) portion. The age of the SLC portion and the MLC portion may differ, leading potentially to one portion wearing out before the other. In order to avoid this, a controller is configured to receive an age indicator from one or both of the SLC portion and the MLC portion, determine, based on the age indicator, whether to modify operation of the SLC portion and/or the MLC portion, and in response to determining to modifying operation, modify the operation of the at least one of the SLC portion or the MLC portion. The modification of the operation may thus balance wear between the SLC and MLC portions, thereby potentially extending the life of the flash memory device.
摘要翻译：公开了一种用于闪存设备中的SLC-MLC磨损平衡的方法和系统。闪速存储器件包括单级单元（SLC）部分和多级单元（MLC）部分。 SLC部分和MLC部分的时代可能不同，潜在地导致在另一部分之前磨损的部分。为了避免这种情况，控制器被配置为从SLC部分和MLC部分中的一个或两个接收年龄指示符，基于年龄指示符确定是否修改SLC部分和/或MLC部分的操作并且响应于确定修改操作，修改SLC部分或MLC部分中的至少一个的操作。因此，操作的修改可以平衡SLC和MLC部分之间的磨损，从而潜在地延长闪存设备的寿命。

2. 发明申请

US20130173844A1 SLC-MLC Wear Balancing 有权
标题翻译： SLC-MLC穿着平衡
公开(公告)号：US20130173844A1
公开(公告)日：2013-07-04
申请号：US13340446
申请日：2011-12-29
申请人： Jian Chen , Sergey Anatolievich Gorobets , Steven Sprouse
发明人： Jian Chen , Sergey Anatolievich Gorobets , Steven Sprouse
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： A method and system for SLC-MLC Wear Balancing in a flash memory device is disclosed. The flash memory device includes a single level cell (SLC) portion and a multi-level cell (MLC) portion. The age of the SLC portion and the MLC portion may differ, leading potentially to one portion wearing out before the other. In order to avoid this, a controller is configured to receive an age indicator from one or both of the SLC portion and the MLC portion, determine, based on the age indicator, whether to modify operation of the SLC portion and/or the MLC portion, and in response to determining to modifying operation, modify the operation of the at least one of the SLC portion or the MLC portion. The modification of the operation may thus balance wear between the SLC and MLC portions, thereby potentially extending the life of the flash memory device.
摘要翻译：公开了一种用于闪存设备中的SLC-MLC磨损平衡的方法和系统。闪速存储器件包括单级单元（SLC）部分和多级单元（MLC）部分。 SLC部分和MLC部分的时代可能不同，潜在地导致在另一部分之前磨损的部分。为了避免这种情况，控制器被配置为从SLC部分和MLC部分中的一个或两个接收年龄指示符，基于年龄指示符确定是否修改SLC部分和/或MLC部分的操作并且响应于确定修改操作，修改SLC部分或MLC部分中的至少一个的操作。因此，操作的修改可以平衡SLC和MLC部分之间的磨损，从而潜在地延长闪存设备的寿命。

3. 发明授权

US08775722B2 Storing data in parallel in a flash storage device using on chip page shifting between planes 有权
标题翻译：在闪存存储设备中并行存储数据，使用片上页面在平面之间切换
公开(公告)号：US08775722B2
公开(公告)日：2014-07-08
申请号：US13341543
申请日：2011-12-30
申请人： Steven Sprouse , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Sergey Anatolievich Gorobets
IPC分类号： G06F12/00
CPC分类号： G11C7/1012 , G11C11/5621 , G11C16/10
摘要： Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).
摘要翻译：本文公开了用于将数据存储在存储器件中的方法和系统。使用平面交错并行写入多页数据。例如，在四平面写入中，按照以下顺序写入第一组四页：0,1,2,3。在平面交织之后的第二组四页被写入随后的后续步骤：7，写入数据后，读取写入数据的页面，如果需要，页面交换，然后写入存储器的另一部分（如MLC）。

4. 发明申请

US20130173847A1 Metablock Size Reduction Using on Chip Page Swapping Between Planes 有权
标题翻译：使用片上页面交换平面之间的元块大小缩小
公开(公告)号：US20130173847A1
公开(公告)日：2013-07-04
申请号：US13341543
申请日：2011-12-30
申请人： Steven Sprouse , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Sergey Anatolievich Gorobets
IPC分类号： G06F12/00
CPC分类号： G11C7/1012 , G11C11/5621 , G11C16/10
摘要： Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).
摘要翻译：本文公开了用于将数据存储在存储器件中的方法和系统。使用平面交错并行写入多页数据。例如，在四平面写入中，按照以下顺序写入第一组四页：0,1,2,3。在平面交织之后的第二组四页被写入随后的后续步骤：7，写入数据后，读取写入数据的页面，如果需要，页面交换，然后写入存储器的另一部分（如MLC）。

5. 发明申请

US20110153913A1 Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data 有权
标题翻译：使用片上数据折叠的多档位控制的非易失性存储器
公开(公告)号：US20110153913A1
公开(公告)日：2011-06-23
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

6. 发明授权

US08634239B2 Hybrid multi-level cell programming sequences 有权
标题翻译：混合多级单元编程序列
公开(公告)号：US08634239B2
公开(公告)日：2014-01-21
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

7. 发明申请

US20130170293A1 HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES 有权
标题翻译：混合多级细胞编程序列
公开(公告)号：US20130170293A1
公开(公告)日：2013-07-04
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

8. 发明授权

US09063862B2 Expandable data cache 有权
标题翻译：可扩展数据缓存
公开(公告)号：US09063862B2
公开(公告)日：2015-06-23
申请号：US13109777
申请日：2011-05-17
申请人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
发明人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0871 , G06F12/0897 , G06F2212/2022 , G06F2212/214 , G06F2212/2515 , G06F2212/466 , G06F2212/6012
摘要： A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations.
摘要翻译：公开了一种用于存储设备中的高速缓存管理的方法和系统。存储设备中的未使用的存储器的一部分用于临时数据高速缓存，使得可以使用两级缓存（诸如永久数据高速缓存和临时数据高速缓存）。存储设备可以管理临时数据高速缓存，以便在临时数据高速缓存中保持干净的条目。以这种方式，与临时数据高速缓存相关联的存储区域可以立即回收并重新筛选以用于不同的目的，而不需要无关的复制操作。

9. 发明授权

US08468294B2 Non-volatile memory with multi-gear control using on-chip folding of data 有权
标题翻译：具有多档位控制的非易失性存储使用片上数据折叠
公开(公告)号：US08468294B2
公开(公告)日：2013-06-18
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F3/06 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

10. 发明申请

US20120297140A1 EXPANDABLE DATA CACHE 有权
标题翻译：可扩展数据缓存
公开(公告)号：US20120297140A1
公开(公告)日：2012-11-22
申请号：US13109777
申请日：2011-05-17
申请人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
发明人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
IPC分类号： G06F12/12
CPC分类号： G06F12/0871 , G06F12/0897 , G06F2212/2022 , G06F2212/214 , G06F2212/2515 , G06F2212/466 , G06F2212/6012
摘要： A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations.
摘要翻译：公开了一种用于存储设备中的高速缓存管理的方法和系统。存储设备中的未使用的存储器的一部分用于临时数据高速缓存，使得可以使用两级缓存（诸如永久数据高速缓存和临时数据高速缓存）。存储设备可以管理临时数据高速缓存，以便在临时数据高速缓存中保持干净的条目。以这种方式，与临时数据高速缓存相关联的存储区域可以立即回收并重新筛选以用于不同的目的，而不需要无关的复制操作。

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